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| author | Robert Jarzmik <robert.jarzmik@free.fr> | 2013-06-24 04:52:51 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-07-01 08:49:11 +0000 |
| commit | 9188a9bc680702a10ed5ccd4a748829816fe172d (patch) | |
| tree | c1e6a52d38442174f276b50f320d03ee5aecc3eb /Doxyfile.in | |
| parent | 12e25f34ebc9a62ac327d51229c32deda009addc (diff) | |
| download | riscv-openocd-9188a9bc680702a10ed5ccd4a748829816fe172d.zip riscv-openocd-9188a9bc680702a10ed5ccd4a748829816fe172d.tar.gz riscv-openocd-9188a9bc680702a10ed5ccd4a748829816fe172d.tar.bz2 | |
target: xscale make reset init work properly
On XScale architecture, to write debug control register DCSR
and activate JTAG debug (ie. to choose Halt Mode), the
enabling can only be done while the board is held in reset
state (ie. PXAxx #RST line held low).
The current implementation writes to the register before
asserting the SRST line. Swap the order to activate the SRST
line before writing to DCSR.
Change-Id: I914b9d53d39bdeb5fe4ee5e11068cafafe0da4d2
Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Reviewed-on: http://openocd.zylin.com/1458
Tested-by: jenkins
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'Doxyfile.in')
0 files changed, 0 insertions, 0 deletions