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authorEvgeniy Naydanov <109669442+en-sc@users.noreply.github.com>2024-08-08 15:25:15 +0300
committerGitHub <noreply@github.com>2024-08-08 15:25:15 +0300
commit9a23c9e67978f77d9166102cefc7b537b714b561 (patch)
treeef8619af96f4c88edebd9affef3e962c8a6ab230
parent5afed58fcdb67ff87842dad9c3ab7f73ca0c8cd8 (diff)
parent205e4c8b9753841ec900a9b1c199d8955ad76ffb (diff)
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Merge pull request #1104 from TommyMurphyTM1234/fix-include-guardsHEADlatestriscv
Align include guards with OpenOCD coding guidelines
-rw-r--r--src/target/riscv/asm.h6
-rw-r--r--src/target/riscv/batch.h6
-rw-r--r--src/target/riscv/debug_reg_printer.h5
-rw-r--r--src/target/riscv/field_helpers.h6
-rw-r--r--src/target/riscv/gdb_regs.h6
-rw-r--r--src/target/riscv/opcodes.h4
-rw-r--r--src/target/riscv/program.h6
-rw-r--r--src/target/riscv/riscv-011.h2
-rw-r--r--src/target/riscv/riscv-011_reg.h6
-rw-r--r--src/target/riscv/riscv-013.h2
-rw-r--r--src/target/riscv/riscv-013_reg.h6
-rw-r--r--src/target/riscv/riscv.h6
12 files changed, 35 insertions, 26 deletions
diff --git a/src/target/riscv/asm.h b/src/target/riscv/asm.h
index 6ceb8c9..828cd86 100644
--- a/src/target/riscv/asm.h
+++ b/src/target/riscv/asm.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef TARGET__RISCV__ASM_H
-#define TARGET__RISCV__ASM_H
+#ifndef OPENOCD_TARGET_RISCV_ASM_H
+#define OPENOCD_TARGET_RISCV_ASM_H
#include "riscv.h"
@@ -37,4 +37,4 @@ static uint32_t store(const struct target *target, unsigned int src,
return 0; /* Silence -Werror=return-type */
}
-#endif
+#endif /* OPENOCD_TARGET_RISCV_ASM_H */
diff --git a/src/target/riscv/batch.h b/src/target/riscv/batch.h
index f00e1c1..660a63f 100644
--- a/src/target/riscv/batch.h
+++ b/src/target/riscv/batch.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef TARGET__RISCV__SCANS_H
-#define TARGET__RISCV__SCANS_H
+#ifndef OPENOCD_TARGET_RISCV_BATCH_H
+#define OPENOCD_TARGET_RISCV_BATCH_H
#include "target/target.h"
#include "jtag/jtag.h"
@@ -234,4 +234,4 @@ bool riscv_batch_was_batch_busy(const struct riscv_batch *batch);
void riscv_log_dmi_scan(const struct target *target, int idle,
const struct scan_field *field);
-#endif
+#endif /* OPENOCD_TARGET_RISCV_BATCH_H */
diff --git a/src/target/riscv/debug_reg_printer.h b/src/target/riscv/debug_reg_printer.h
index 98226b7..5089ff8 100644
--- a/src/target/riscv/debug_reg_printer.h
+++ b/src/target/riscv/debug_reg_printer.h
@@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H
+#define OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H
+
#include "debug_defines.h"
enum riscv_debug_reg_show {
@@ -33,3 +36,5 @@ enum riscv_debug_reg_show {
unsigned int riscv_debug_reg_to_s(char *buf, enum riscv_debug_reg_ordinal reg_ordinal,
riscv_debug_reg_ctx_t context, uint64_t value,
enum riscv_debug_reg_show show);
+
+#endif /* OPENOCD_TARGET_RISCV_DEBUG_REG_PRINTER_H */
diff --git a/src/target/riscv/field_helpers.h b/src/target/riscv/field_helpers.h
index 16578f1..abf19f6 100644
--- a/src/target/riscv/field_helpers.h
+++ b/src/target/riscv/field_helpers.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef FIELD_HELPERS_H
-#define FIELD_HELPERS_H
+#ifndef OPENOCD_TARGET_RISCV_FIELD_HELPERS_H
+#define OPENOCD_TARGET_RISCV_FIELD_HELPERS_H
#include <stdint.h>
#include <assert.h>
@@ -44,4 +44,4 @@ static inline uint32_t field_value32(uint32_t mask, uint32_t val)
return set_field32(0, mask, val);
}
-#endif
+#endif /* OPENOCD_TARGET_RISCV_FIELD_HELPERS_H */
diff --git a/src/target/riscv/gdb_regs.h b/src/target/riscv/gdb_regs.h
index d606f73..0d03929 100644
--- a/src/target/riscv/gdb_regs.h
+++ b/src/target/riscv/gdb_regs.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef TARGET__RISCV__GDB_REGS_H
-#define TARGET__RISCV__GDB_REGS_H
+#ifndef OPENOCD_TARGET_RISCV_GDB_REGS_H
+#define OPENOCD_TARGET_RISCV_GDB_REGS_H
#include "encoding.h"
@@ -125,4 +125,4 @@ enum gdb_regno {
GDB_REGNO_COUNT
};
-#endif
+#endif /* OPENOCD_TARGET_RISCV_GDB_REGS_H */
diff --git a/src/target/riscv/opcodes.h b/src/target/riscv/opcodes.h
index 59c3413..99ae90f 100644
--- a/src/target/riscv/opcodes.h
+++ b/src/target/riscv/opcodes.h
@@ -1,5 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#ifndef OPENOCD_TARGET_RISCV_OPCODES_H
+#define OPENOCD_TARGET_RISCV_OPCODES_H
+
#include "encoding.h"
#define ZERO 0
@@ -339,3 +342,4 @@ static uint32_t vslide1down_vx(unsigned int vd, unsigned int vs2,
return ((vm & 1) << 25) | inst_rs2(vs2) | inst_rs1(rs1) | inst_rd(vd) | MATCH_VSLIDE1DOWN_VX;
}
+#endif /* OPENOCD_TARGET_RISCV_OPCODES_H */
diff --git a/src/target/riscv/program.h b/src/target/riscv/program.h
index 93dbdbf..91f0dab 100644
--- a/src/target/riscv/program.h
+++ b/src/target/riscv/program.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef TARGET__RISCV__PROGRAM_H
-#define TARGET__RISCV__PROGRAM_H
+#ifndef OPENOCD_TARGET_RISCV_PROGRAM_H
+#define OPENOCD_TARGET_RISCV_PROGRAM_H
#include "riscv.h"
@@ -77,4 +77,4 @@ int riscv_program_ebreak(struct riscv_program *p);
int riscv_program_addi(struct riscv_program *p, enum gdb_regno d, enum gdb_regno s, int16_t i);
-#endif
+#endif /* OPENOCD_TARGET_RISCV_PROGRAM_H */
diff --git a/src/target/riscv/riscv-011.h b/src/target/riscv/riscv-011.h
index 8d1d06a..bbbc194 100644
--- a/src/target/riscv/riscv-011.h
+++ b/src/target/riscv/riscv-011.h
@@ -12,4 +12,4 @@ int riscv011_get_register(struct target *target, riscv_reg_t *value,
int riscv011_set_register(struct target *target, enum gdb_regno regid,
riscv_reg_t value);
-#endif /*OPENOCD_TARGET_RISCV_RISCV_011_H*/
+#endif /* OPENOCD_TARGET_RISCV_RISCV_011_H */
diff --git a/src/target/riscv/riscv-011_reg.h b/src/target/riscv/riscv-011_reg.h
index ee00c9b..4f7911a 100644
--- a/src/target/riscv/riscv-011_reg.h
+++ b/src/target/riscv/riscv-011_reg.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef OPENOCD_TARGET_RISCV_RISCV_REG_011_H
-#define OPENOCD_TARGET_RISCV_RISCV_REG_011_H
+#ifndef OPENOCD_TARGET_RISCV_RISCV_011_REG_H
+#define OPENOCD_TARGET_RISCV_RISCV_011_REG_H
#include "target/target.h"
@@ -16,4 +16,4 @@
*/
int riscv011_reg_init_all(struct target *target);
-#endif /*OPENOCD_TARGET_RISCV_RISCV_REG_011_H*/
+#endif /* OPENOCD_TARGET_RISCV_RISCV_011_REG_H */
diff --git a/src/target/riscv/riscv-013.h b/src/target/riscv/riscv-013.h
index be508f7..f39393c 100644
--- a/src/target/riscv/riscv-013.h
+++ b/src/target/riscv/riscv-013.h
@@ -20,4 +20,4 @@ int riscv013_set_register(struct target *target, enum gdb_regno rid,
int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
const uint8_t *value);
-#endif /*OPENOCD_TARGET_RISCV_RISCV_013_H*/
+#endif /* OPENOCD_TARGET_RISCV_RISCV_013_H */
diff --git a/src/target/riscv/riscv-013_reg.h b/src/target/riscv/riscv-013_reg.h
index 2bdaaa0..e7a9447 100644
--- a/src/target/riscv/riscv-013_reg.h
+++ b/src/target/riscv/riscv-013_reg.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef OPENOCD_TARGET_RISCV_RISCV_REG_013_H
-#define OPENOCD_TARGET_RISCV_RISCV_REG_013_H
+#ifndef OPENOCD_TARGET_RISCV_RISCV_013_REG_H
+#define OPENOCD_TARGET_RISCV_RISCV_013_REG_H
#include "target/target.h"
#include "gdb_regs.h"
@@ -28,4 +28,4 @@ int riscv013_reg_init_all(struct target *target);
*/
int riscv013_reg_save(struct target *target, enum gdb_regno regid);
-#endif /*OPENOCD_TARGET_RISCV_RISCV_REG_013_H*/
+#endif /* OPENOCD_TARGET_RISCV_RISCV_013_REG_H */
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index b29d209..a25aac8 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
-#ifndef RISCV_H
-#define RISCV_H
+#ifndef OPENOCD_TARGET_RISCV_RISCV_H
+#define OPENOCD_TARGET_RISCV_RISCV_H
struct riscv_program;
@@ -433,4 +433,4 @@ int riscv_write_by_any_size(struct target *target, target_addr_t address, uint32
int riscv_interrupts_disable(struct target *target, uint64_t ie_mask, uint64_t *old_mstatus);
int riscv_interrupts_restore(struct target *target, uint64_t old_mstatus);
-#endif
+#endif /* OPENOCD_TARGET_RISCV_RISCV_H */