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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-15 14:57:21 +0100 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2017-02-24 09:15:18 +0000 |
| commit | 6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c (patch) | |
| tree | 75627cf6d44965644737e7de93eb69e71ad1af8d | |
| parent | 095ff3d2103f9e8089b5b1fb0816d43874014e08 (diff) | |
| download | riscv-openocd-6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c.zip riscv-openocd-6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c.tar.gz riscv-openocd-6fb9f2e3ee05d8ff6241e6d61f7de0e71afeb45c.tar.bz2 | |
armv8: factor out generic bit set/clr for debug registers
introduce armv8_set_dbgreg_bits() function to make register
bit-field modifications easier to read.
Change-Id: I6b06f66262587fd301d848c9e0645e8327653de7
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/3989
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
| -rw-r--r-- | src/target/aarch64.c | 18 | ||||
| -rw-r--r-- | src/target/armv8.c | 21 | ||||
| -rw-r--r-- | src/target/armv8.h | 1 |
3 files changed, 23 insertions, 17 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 5dd6d7a..65a5278 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -238,23 +238,7 @@ static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug) static int aarch64_set_dscr_bits(struct target *target, unsigned long bit_mask, unsigned long value) { struct armv8_common *armv8 = target_to_armv8(target); - uint32_t dscr; - - /* Read DSCR */ - int retval = mem_ap_read_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DSCR, &dscr); - if (ERROR_OK != retval) - return retval; - - /* clear bitfield */ - dscr &= ~bit_mask; - /* put new value */ - dscr |= value & bit_mask; - - /* write new DSCR */ - retval = mem_ap_write_atomic_u32(armv8->debug_ap, - armv8->debug_base + CPUV8_DBG_DSCR, dscr); - return retval; + return armv8_set_dbgreg_bits(armv8, CPUV8_DBG_DSCR, bit_mask, value); } static struct target *get_aarch64(struct target *target, int32_t coreid) diff --git a/src/target/armv8.c b/src/target/armv8.c index 00ab6ed..2f1d5c1 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1292,3 +1292,24 @@ int armv8_get_gdb_reg_list(struct target *target, } } } + +int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value) +{ + uint32_t tmp; + + /* Read register */ + int retval = mem_ap_read_atomic_u32(armv8->debug_ap, + armv8->debug_base + reg, &tmp); + if (ERROR_OK != retval) + return retval; + + /* clear bitfield */ + tmp &= ~mask; + /* put new value */ + tmp |= value & mask; + + /* write new value */ + retval = mem_ap_write_atomic_u32(armv8->debug_ap, + armv8->debug_base + reg, tmp); + return retval; +} diff --git a/src/target/armv8.h b/src/target/armv8.h index 3b2fc59..1cb3a3b 100644 --- a/src/target/armv8.h +++ b/src/target/armv8.h @@ -307,6 +307,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode) } void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64); +int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value); extern const struct command_registration armv8_command_handlers[]; |