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author | Tim Newsome <tim@sifive.com> | 2018-04-18 13:11:08 -0700 |
---|---|---|
committer | GitHub <noreply@github.com> | 2018-04-18 13:11:08 -0700 |
commit | 69a426038d5366517d88ae88ecacfcc9472efef2 (patch) | |
tree | 5b444d0bf2d49b0ebac43298721b6ab0fc320cf8 | |
parent | a9cf934c890d416b87bfbbd7bf2ac796535f19f4 (diff) | |
download | riscv-openocd-69a426038d5366517d88ae88ecacfcc9472efef2.zip riscv-openocd-69a426038d5366517d88ae88ecacfcc9472efef2.tar.gz riscv-openocd-69a426038d5366517d88ae88ecacfcc9472efef2.tar.bz2 |
Enforce OpenOCD style guide. (#239)
* Enforce OpenOCD style guide.
Change-Id: I579a9f54ed22a774bf52f6aa5bc13bcbd2e82cd8
* Fail if `git diff` fails
Change-Id: I57256b0a24247f6123cb0e25a89c1b59867cb3f9
* Maybe every line gets its own shell?
Change-Id: I1a6f83e9f3d7cfd39f8933f0dba13c3cf76f71f6
* Maybe this will error properly.
Change-Id: I50803cfc229e61158569fb6b609195f7191ecac9
* Take different approach than merge-base
Change-Id: I345cbc4eecc4755c7127e8e36e403f7b727010b1
* Fix style issues.
Change-Id: I90e71f710858524812d0ab160b25c486b7b099e7
-rw-r--r-- | .travis.yml | 6 | ||||
-rw-r--r-- | src/target/riscv/riscv-011.c | 6 | ||||
-rw-r--r-- | src/target/riscv/riscv-013.c | 12 | ||||
-rw-r--r-- | src/target/riscv/riscv.c | 8 |
4 files changed, 16 insertions, 16 deletions
diff --git a/.travis.yml b/.travis.yml index 37a5993..2aeed08 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,5 +50,11 @@ matrix: - binutils-mingw-w64-i686 gcc-mingw-w64-i686 g++-mingw-w64-i686 script: + # Ideally we'd diff back to where we either branched off OpenOCD or master, + # or riscv. But that's tricky, and the default git clone only gets the last + # 50 changes any case. Most merges won't consist of more than 40 changes, + # so this should work fine most of the time, and be a lot better than not + # checking at all. + - git diff HEAD~40 | ./tools/scripts/checkpatch.pl --no-signoff - - ./bootstrap && ./configure --enable-remote-bitbang --enable-jtag_vpi $CONFIGURE_ARGS && make - file src/$EXECUTABLE diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index b450d2b..4322f7b 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -455,12 +455,12 @@ static uint64_t dbus_read(struct target *target, uint16_t address) uint64_t value; dbus_status_t status; uint16_t address_in; - + /* If the previous read/write was to the same address, we will get the read data * from the previous access. * While somewhat nonintuitive, this is an efficient way to get the data. */ - + unsigned i = 0; do { status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0); @@ -680,7 +680,7 @@ static bits_t read_bits(struct target *target) } increase_dbus_busy_delay(target); } else if (status == DBUS_STATUS_FAILED) { - // TODO: return an actual error + /* TODO: return an actual error */ return err_result; } } while (status == DBUS_STATUS_BUSY && i++ < 256); diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 8946948..cec01f3 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -249,9 +249,8 @@ static dm013_info_t *get_dm(struct target *target) info->dm = dm; target_list_t *target_entry; list_for_each_entry(target_entry, &dm->target_list, list) { - if (target_entry->target == target) { + if (target_entry->target == target) return dm; - } } target_entry = calloc(1, sizeof(*target_entry)); target_entry->target = target; @@ -1760,19 +1759,16 @@ static int sb_write_address(struct target *target, target_addr_t address) RISCV013_INFO(info); unsigned sbasize = get_field(info->sbcs, DMI_SBCS_SBASIZE); /* There currently is no support for >64-bit addresses in OpenOCD. */ - if (sbasize > 96) { + if (sbasize > 96) dmi_write(target, DMI_SBADDRESS3, 0); - } - if (sbasize > 64) { + if (sbasize > 64) dmi_write(target, DMI_SBADDRESS2, 0); - } - if (sbasize > 32) { + if (sbasize > 32) #if BUILD_TARGET64 dmi_write(target, DMI_SBADDRESS1, address >> 32); #else dmi_write(target, DMI_SBADDRESS1, 0); #endif - } return dmi_write(target, DMI_SBADDRESS0, address); } diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index aea6d7a..4a0bc66 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1105,16 +1105,14 @@ int riscv_openocd_resume( while (watchpoint && result == ERROR_OK) { LOG_DEBUG("watchpoint %d: set=%d", i, watchpoint->set); trigger_temporarily_cleared[i] = watchpoint->set; - if (watchpoint->set) { + if (watchpoint->set) result = riscv_remove_watchpoint(target, watchpoint); - } watchpoint = watchpoint->next; i++; } - if (result == ERROR_OK) { + if (result == ERROR_OK) result = riscv_step_rtos_hart(target); - } watchpoint = target->watchpoints; i = 0; @@ -1217,7 +1215,7 @@ COMMAND_HANDLER(riscv_set_scratch_ram) return ERROR_OK; } - // TODO: use COMMAND_PARSE_NUMBER + /* TODO: use COMMAND_PARSE_NUMBER */ long long unsigned int address; int result = sscanf(CMD_ARGV[0], "%llx", &address); if (result != (int) strlen(CMD_ARGV[0])) { |