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author | Antonio Borneo <borneo.antonio@gmail.com> | 2021-05-05 12:27:11 +0200 |
---|---|---|
committer | Antonio Borneo <borneo.antonio@gmail.com> | 2021-05-22 10:04:12 +0100 |
commit | 510df38407da25aa0fa7427d26b9253455885d9b (patch) | |
tree | 0a8daa3246ae10b2146842e4d6ad79a755483b7c | |
parent | 936cff887abf116427802c4f07096fca1f2b1d88 (diff) | |
download | riscv-openocd-510df38407da25aa0fa7427d26b9253455885d9b.zip riscv-openocd-510df38407da25aa0fa7427d26b9253455885d9b.tar.gz riscv-openocd-510df38407da25aa0fa7427d26b9253455885d9b.tar.bz2 |
target/arm_dpm: rename 'wp_pc' as 'wp_addr'
The field 'wp_pc' was originally introduced in commit 55eeea7fceb6
("ARMv7a/Cortex-A8: report watchpoint trigger insn") in end 2009
to contain the address of the instruction which triggered a
watchpoint. Later on with commit 651b861d5d5f ("target/aarch64:
Add watchpoint support") it has been reused in to hold directly
the memory address that triggered a watchpoint.
Rename 'wp_pc' as 'wp_addr' and change its doxygen description.
While there, fix the format string to print the field.
Change-Id: I2e5ced1497e4a6fb6b38f91e881807512e8d8c47
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6204
Tested-by: jenkins
Reviewed-by: Liming Sun <limings@nvidia.com>
-rw-r--r-- | src/target/aarch64.c | 6 | ||||
-rw-r--r-- | src/target/arm11.c | 3 | ||||
-rw-r--r-- | src/target/arm_dpm.c | 2 | ||||
-rw-r--r-- | src/target/arm_dpm.h | 8 | ||||
-rw-r--r-- | src/target/armv7a.c | 3 | ||||
-rw-r--r-- | src/target/armv8.c | 3 | ||||
-rw-r--r-- | src/target/armv8_dpm.c | 2 |
7 files changed, 14 insertions, 13 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index 4ba92c8..e6eb2ca 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -1856,7 +1856,7 @@ int aarch64_hit_watchpoint(struct target *target, uint64_t exception_address; struct watchpoint *wp; - exception_address = armv8->dpm.wp_pc; + exception_address = armv8->dpm.wp_addr; if (exception_address == 0xFFFFFFFF) return ERROR_FAIL; @@ -1867,12 +1867,12 @@ int aarch64_hit_watchpoint(struct target *target, /* the EDWAR value needs to have 8 added to it so we add */ /* that check as well not sure if that is a core bug) */ /**********************************************************/ - for (exception_address = armv8->dpm.wp_pc; exception_address <= (armv8->dpm.wp_pc + 8); + for (exception_address = armv8->dpm.wp_addr; exception_address <= (armv8->dpm.wp_addr + 8); exception_address += 8) { for (wp = target->watchpoints; wp; wp = wp->next) { if ((exception_address >= wp->address) && (exception_address < (wp->address + wp->length))) { *hit_watchpoint = wp; - if (exception_address != armv8->dpm.wp_pc) + if (exception_address != armv8->dpm.wp_addr) LOG_DEBUG("watchpoint hit required EDWAR to be increased by 8"); return ERROR_OK; } diff --git a/src/target/arm11.c b/src/target/arm11.c index 68d4e18..ff125d0 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -355,8 +355,7 @@ static int arm11_arch_state(struct target *target) /* REVISIT also display ARM11-specific MMU and cache status ... */ if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) arm11->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, arm11->dpm.wp_addr); return retval; } diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 6bfe355..e172fad 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -1010,7 +1010,7 @@ void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t addr) /* ?? */ break; } - dpm->wp_pc = addr; + dpm->wp_addr = addr; } /*----------------------------------------------------------------------*/ diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h index 8270782..80587f5 100644 --- a/src/target/arm_dpm.h +++ b/src/target/arm_dpm.h @@ -137,8 +137,12 @@ struct arm_dpm { struct dpm_bp *dbp; struct dpm_wp *dwp; - /** Address of the instruction which triggered a watchpoint. */ - target_addr_t wp_pc; + /** + * Target dependent watchpoint address. + * Either the address of the instruction which triggered a watchpoint + * or the memory address whose access triggered a watchpoint. + */ + target_addr_t wp_addr; /** Recent value of DSCR. */ uint32_t dscr; diff --git a/src/target/armv7a.c b/src/target/armv7a.c index abca335..5c9f308 100644 --- a/src/target/armv7a.c +++ b/src/target/armv7a.c @@ -571,8 +571,7 @@ int armv7a_arch_state(struct target *target) if (arm->core_mode == ARM_MODE_ABT) armv7a_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) armv7a->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv7a->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/armv8.c b/src/target/armv8.c index 6bf3b11..e209e88 100644 --- a/src/target/armv8.c +++ b/src/target/armv8.c @@ -1169,8 +1169,7 @@ int armv8_arch_state(struct target *target) armv8_show_fault_registers(target); if (target->debug_reason == DBG_REASON_WATCHPOINT) - LOG_USER("Watchpoint triggered at PC %#08x", - (unsigned) armv8->dpm.wp_pc); + LOG_USER("Watchpoint triggered at PC " TARGET_ADDR_FMT, armv8->dpm.wp_addr); return ERROR_OK; } diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c index e7d0f86..a7b4f1d 100644 --- a/src/target/armv8_dpm.c +++ b/src/target/armv8_dpm.c @@ -1297,7 +1297,7 @@ void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t addr) LOG_DEBUG("Unknown core_state"); break; } - dpm->wp_pc = addr; + dpm->wp_addr = addr; } /* |