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| author | Peter Collingbourne <pcc@google.com> | 2023-10-17 19:04:00 -0700 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2023-11-18 11:21:38 +0000 |
| commit | 393da819b14c62d267cf5ec86bc511c187e1af18 (patch) | |
| tree | 3b57dbdcc6b9b970f60623ea8b3fd7a3a248cf82 | |
| parent | ee96a95d44322aa109847e35b86aed5ad3066cf8 (diff) | |
| download | riscv-openocd-393da819b14c62d267cf5ec86bc511c187e1af18.zip riscv-openocd-393da819b14c62d267cf5ec86bc511c187e1af18.tar.gz riscv-openocd-393da819b14c62d267cf5ec86bc511c187e1af18.tar.bz2 | |
aarch64: Use 64-bit reads/writes to access SCTLR_EL1
We were previously inadvertently clearing the top 32 bits of SCTLR_EL1
during read_memory/write_memory as a result of using 32-bit operations
to access the register and because the fields used to temporarily
store the register were 32-bit. Fix it.
Change-Id: I657d7f949e1f7ab6bf90609e3f91cae09cade31a
Signed-off-by: Peter Collingbourne <pcc@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7939
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/target/aarch64.c | 8 | ||||
| -rw-r--r-- | src/target/aarch64.h | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/target/aarch64.c b/src/target/aarch64.c index db60243..1c056a0 100644 --- a/src/target/aarch64.c +++ b/src/target/aarch64.c @@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg); + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg); if (retval != ERROR_OK) return retval; @@ -182,7 +182,7 @@ static int aarch64_mmu_modify(struct target *target, int enable) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, + retval = armv8->dpm.instr_write_data_r0_64(&armv8->dpm, instr, aarch64->system_control_reg_curr); if (target_mode != ARM_MODE_ANY) @@ -1055,14 +1055,14 @@ static int aarch64_post_debug_entry(struct target *target) if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, target_mode); - retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg); + retval = armv8->dpm.instr_read_data_r0_64(&armv8->dpm, instr, &aarch64->system_control_reg); if (retval != ERROR_OK) return retval; if (target_mode != ARM_MODE_ANY) armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY); - LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg); + LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg); aarch64->system_control_reg_curr = aarch64->system_control_reg; if (armv8->armv8_mmu.armv8_cache.info == -1) { diff --git a/src/target/aarch64.h b/src/target/aarch64.h index 2721fe7..b265e82 100644 --- a/src/target/aarch64.h +++ b/src/target/aarch64.h @@ -43,8 +43,8 @@ struct aarch64_common { struct armv8_common armv8_common; /* Context information */ - uint32_t system_control_reg; - uint32_t system_control_reg_curr; + uint64_t system_control_reg; + uint64_t system_control_reg_curr; /* Breakpoint register pairs */ int brp_num_context; |