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| author | Megan Wachs <megan@sifive.com> | 2018-04-24 09:49:06 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2018-04-24 10:24:01 -0700 |
| commit | 3715f207c0c16fcdbaf01a36dd085423a19d24f2 (patch) | |
| tree | 3af43713f2f753e9e1ea512d5325a2bb5ba1164d | |
| parent | dc8c5eeac9952565fd7133c900229dceb576c29c (diff) | |
| download | riscv-openocd-3715f207c0c16fcdbaf01a36dd085423a19d24f2.zip riscv-openocd-3715f207c0c16fcdbaf01a36dd085423a19d24f2.tar.gz riscv-openocd-3715f207c0c16fcdbaf01a36dd085423a19d24f2.tar.bz2 | |
fespi: flag an error if offset can't be handled in 3B mode
| -rw-r--r-- | src/flash/nor/fespi.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c index f6827e3..6df0d38 100644 --- a/src/flash/nor/fespi.c +++ b/src/flash/nor/fespi.c @@ -436,6 +436,12 @@ static int slow_fespi_write_buffer(struct flash_bank *bank, uint32_t ctrl_base = fespi_info->ctrl_base; uint32_t ii; + if (offset & 0xFF000000) { + LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x", + offset); + return ERROR_FAIL; + } + /* TODO!!! assert that len < page size */ fespi_tx(bank, SPIFLASH_WRITE_ENABLE); @@ -769,6 +775,12 @@ static void as_add_set_dir(struct algorithm_steps *as, bool dir) static int steps_add_buffer_write(struct algorithm_steps *as, const uint8_t *buffer, uint32_t chip_offset, uint32_t len) { + if (chip_offset & 0xFF000000) { + LOG_ERROR("FESPI interface does not support greater than 3B addressing, can't write to offset 0x%x", + chip_offset); + return ERROR_FAIL; + } + as_add_tx1(as, SPIFLASH_WRITE_ENABLE); as_add_txwm_wait(as); as_add_write_reg(as, FESPI_REG_CSMODE, FESPI_CSMODE_HOLD); |