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author | Tim Newsome <tim@sifive.com> | 2018-05-22 14:39:28 -0700 |
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committer | GitHub <noreply@github.com> | 2018-05-22 14:39:28 -0700 |
commit | c3ffbc66e6f3a5c005bc8b92380b34108ae649bb (patch) | |
tree | 97f6d352d72f7425ad42519ca29299729836f954 | |
parent | 6875379089a6d5de41a9f879872f73e86b88fca2 (diff) | |
parent | 0ad060d97a36e4a5c2d7bf1862d5ad52f6de9e86 (diff) | |
download | riscv-openocd-c3ffbc66e6f3a5c005bc8b92380b34108ae649bb.zip riscv-openocd-c3ffbc66e6f3a5c005bc8b92380b34108ae649bb.tar.gz riscv-openocd-c3ffbc66e6f3a5c005bc8b92380b34108ae649bb.tar.bz2 |
Merge pull request #257 from riscv/comment
Comment riscv_set_register, register_write_direct
-rw-r--r-- | src/target/riscv/riscv-013.c | 4 | ||||
-rw-r--r-- | src/target/riscv/riscv.c | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index b150b13..12194d6 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1056,6 +1056,10 @@ static unsigned register_size(struct target *target, unsigned number) return riscv_xlen(target); } +/** + * Immediately write the new value to the requested register. This mechanism + * bypasses any caches. + */ static int register_write_direct(struct target *target, unsigned number, uint64_t value) { diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 88d4b92..39f4903 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1770,6 +1770,10 @@ bool riscv_has_register(struct target *target, int hartid, int regid) return 1; } +/** + * This function is called when the debug user wants to change the value of a + * register. The new value may be cached, and may not be written until the hart + * is resumed. */ int riscv_set_register(struct target *target, enum gdb_regno r, riscv_reg_t v) { return riscv_set_register_on_hart(target, riscv_current_hartid(target), r, v); |