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| author | Megan Wachs <megan@sifive.com> | 2018-05-16 22:29:45 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2018-05-16 22:29:45 -0700 |
| commit | 9a5a5c2dc98a206ef3ad764904a690a0deed715c (patch) | |
| tree | b4ef9d3ed814aed1ae7d03f801985d78b4aab3c2 | |
| parent | 5f50e25f1518a29dce72f9910b62f8e99fdfddeb (diff) | |
| parent | 802c3b4003992455a6480b0aecb48f54e84a8bfc (diff) | |
| download | riscv-openocd-9a5a5c2dc98a206ef3ad764904a690a0deed715c.zip riscv-openocd-9a5a5c2dc98a206ef3ad764904a690a0deed715c.tar.gz riscv-openocd-9a5a5c2dc98a206ef3ad764904a690a0deed715c.tar.bz2 | |
Merge remote-tracking branch 'origin/reset-unexpected-check' into riscv-compliance
| -rw-r--r-- | src/target/riscv/riscv-013.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 29a39f0..8860758 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1648,15 +1648,12 @@ static int deassert_reset(struct target *target) char *operation; uint32_t expected_field; - uint32_t unexpected_field; if (target->reset_halt) { operation = "halt"; expected_field = DMI_DMSTATUS_ALLHALTED; - unexpected_field = DMI_DMSTATUS_ANYRUNNING; } else { operation = "run"; expected_field = DMI_DMSTATUS_ALLRUNNING; - unexpected_field = DMI_DMSTATUS_ANYHALTED; } LOG_DEBUG("Waiting for hart %d to %s out of reset.", index, operation); while (1) { @@ -1669,11 +1666,6 @@ static int deassert_reset(struct target *target) index, riscv_reset_timeout_sec); if (result != ERROR_OK) return result; - if (get_field(dmstatus, unexpected_field)) { - LOG_ERROR("Unexpected hart %d status during reset. dmstatus=0x%x", - index, dmstatus); - return ERROR_FAIL; - } if (get_field(dmstatus, expected_field)) break; if (time(NULL) - start > riscv_reset_timeout_sec) { |