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| author | Darius Rad <darius@bluespec.com> | 2018-05-01 11:44:39 -0400 |
|---|---|---|
| committer | Darius Rad <darius@bluespec.com> | 2018-05-01 11:45:24 -0400 |
| commit | 31494f68a45953b81483c8064ff82e5330dd1a10 (patch) | |
| tree | 0927b6c0dc2208383922a39afb64c338c02d1c05 | |
| parent | cb282e81bc1aabe2147c1f4c199c66fece49681e (diff) | |
| download | riscv-openocd-31494f68a45953b81483c8064ff82e5330dd1a10.zip riscv-openocd-31494f68a45953b81483c8064ff82e5330dd1a10.tar.gz riscv-openocd-31494f68a45953b81483c8064ff82e5330dd1a10.tar.bz2 | |
Properly retry system bus access if busy error was detected.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 3b43ebf..4bf5d50 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1913,6 +1913,7 @@ static int read_memory_bus_v1(struct target *target, target_addr_t address, dmi_write(target, DMI_SBCS, DMI_SBCS_SBBUSYERROR); next_address = sb_read_address(target); info->bus_master_read_delay += info->bus_master_read_delay / 10 + 1; + continue; } unsigned error = get_field(sbcs, DMI_SBCS_SBERROR); @@ -2351,6 +2352,7 @@ static int write_memory_bus_v1(struct target *target, target_addr_t address, dmi_write(target, DMI_SBCS, DMI_SBCS_SBBUSYERROR); next_address = sb_read_address(target); info->bus_master_write_delay += info->bus_master_write_delay / 10 + 1; + continue; } unsigned error = get_field(sbcs, DMI_SBCS_SBERROR); |