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| author | Megan Wachs <megan@sifive.com> | 2017-03-21 23:47:21 -0700 |
|---|---|---|
| committer | Megan Wachs <megan@sifive.com> | 2017-03-21 23:47:21 -0700 |
| commit | 98420e377a946c825960a6d6104c209caa1faf6c (patch) | |
| tree | 9412e52e8c608e9a2821734757ecda78e2fda7c4 | |
| parent | 09da0c812f896a74d3c6c84999483e94b90a6f6b (diff) | |
| download | riscv-openocd-98420e377a946c825960a6d6104c209caa1faf6c.zip riscv-openocd-98420e377a946c825960a6d6104c209caa1faf6c.tar.gz riscv-openocd-98420e377a946c825960a6d6104c209caa1faf6c.tar.bz2 | |
riscv: add missing variable declaration.
| -rw-r--r-- | src/target/riscv/riscv-013.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index c8fc91b..e67d69a 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1860,6 +1860,7 @@ static int read_memory(struct target *target, uint32_t address, dmi_write(target, DMI_ABSTRACTCS, DMI_ABSTRACTCS_CMDERR); dmi_write(target, DMI_ABSTRACTAUTO, 0x1 << DMI_ABSTRACTAUTO_AUTOEXECDATA_OFFSET); + uint32_t abstractcs; for (uint32_t i = 0; i < count; i++) { uint32_t value = dmi_read(target, DMI_DATA0); switch (size) { |