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| author | Tim Newsome <tim@sifive.com> | 2022-11-17 11:27:18 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-11-17 11:41:27 -0800 |
| commit | f1e20767bc9c78b994ecc18f1124e721b169013f (patch) | |
| tree | 073f5a9b9023ad61bbda2deb7a4ae61f2ff6453c | |
| parent | e16d7a5611e6f36d218aed1edfc6f445999eb8ed (diff) | |
| download | riscv-openocd-f1e20767bc9c78b994ecc18f1124e721b169013f.zip riscv-openocd-f1e20767bc9c78b994ecc18f1124e721b169013f.tar.gz riscv-openocd-f1e20767bc9c78b994ecc18f1124e721b169013f.tar.bz2 | |
target/riscv: 0.11, call handle_halt() after step
This ensures that we populate the register cache and set target->state.
Some RISC-V changes had upset the balance.
Change-Id: I47fbf8ebd8fe39fa5b752212080f87e3b7e6e5e5
Signed-off-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | src/target/riscv/riscv-011.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c index 2c4a46e..e38d854 100644 --- a/src/target/riscv/riscv-011.c +++ b/src/target/riscv/riscv-011.c @@ -67,6 +67,8 @@ * to the target. Afterwards use cache_get... to read results. */ +static int handle_halt(struct target *target, bool announce); + #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1))) #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask))) @@ -1192,7 +1194,7 @@ static int full_step(struct target *target, bool announce) return ERROR_FAIL; } } - return ERROR_OK; + return handle_halt(target, announce); } static uint64_t reg_cache_get(struct target *target, unsigned int number) |