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| author | Tim Newsome <tim@sifive.com> | 2023-01-02 13:53:56 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-01-03 10:06:12 -0800 |
| commit | 9efa7775d4a388719b3bc16d79ac5d294eba537a (patch) | |
| tree | 8f69dc44482420f4e4df90b19876fd4ca4af2cca | |
| parent | 6c027e0df486fe4a8495541e9b321259c23c4a00 (diff) | |
| download | riscv-openocd-9efa7775d4a388719b3bc16d79ac5d294eba537a.zip riscv-openocd-9efa7775d4a388719b3bc16d79ac5d294eba537a.tar.gz riscv-openocd-9efa7775d4a388719b3bc16d79ac5d294eba537a.tar.bz2 | |
target/riscv: Read back tdata2 in set_trigger()
Change-Id: I2a9271c66565a4c93de3322e14be8b75577ed1b6
Signed-off-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | src/target/riscv/riscv.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 117e7db..dd5eb71 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -520,7 +520,7 @@ static int find_first_trigger_by_id(struct target *target, int unique_id) static int set_trigger(struct target *target, int idx, riscv_reg_t tdata1, riscv_reg_t tdata2, riscv_reg_t tdata1_ignore_mask) { - riscv_reg_t tdata1_rb; + riscv_reg_t tdata1_rb, tdata2_rb; if (riscv_set_register(target, GDB_REGNO_TSELECT, idx) != ERROR_OK) return ERROR_FAIL; if (riscv_set_register(target, GDB_REGNO_TDATA1, tdata1) != ERROR_OK) @@ -528,16 +528,26 @@ static int set_trigger(struct target *target, int idx, riscv_reg_t tdata1, riscv if (riscv_get_register(target, &tdata1_rb, GDB_REGNO_TDATA1) != ERROR_OK) return ERROR_FAIL; if ((tdata1 & ~tdata1_ignore_mask) != (tdata1_rb & ~tdata1_ignore_mask)) { - LOG_DEBUG("Trigger doesn't support what we need; After writing 0x%" + LOG_TARGET_DEBUG(target, + "Trigger %u doesn't support what we need; After writing 0x%" PRIx64 " to tdata1 it contains 0x%" PRIx64 "; tdata1_ignore_mask=0x%" PRIx64, - tdata1, tdata1_rb, tdata1_ignore_mask); + idx, tdata1, tdata1_rb, tdata1_ignore_mask); riscv_set_register(target, GDB_REGNO_TDATA1, 0); return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; } - LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb); if (riscv_set_register(target, GDB_REGNO_TDATA2, tdata2) != ERROR_OK) return ERROR_FAIL; + if (riscv_get_register(target, &tdata2_rb, GDB_REGNO_TDATA2) != ERROR_OK) + return ERROR_FAIL; + if (tdata2 != tdata2_rb) { + LOG_TARGET_DEBUG(target, + "Trigger %u doesn't support what we need; wrote 0x%" + PRIx64 " to tdata2 but read back 0x%" PRIx64, + idx, tdata2, tdata2_rb); + riscv_set_register(target, GDB_REGNO_TDATA1, 0); + return ERROR_TARGET_RESOURCE_NOT_AVAILABLE; + } return ERROR_OK; } |