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| author | Tim Newsome <tim@sifive.com> | 2023-02-15 09:37:29 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-02-15 09:41:55 -0800 |
| commit | 7c3a77c37aebfe52b3e18e4f568399590debbe4a (patch) | |
| tree | e2c7db3f9a59533f8ba5cfdcd03b5679e5f3b613 | |
| parent | fb3376b7f0279c9ca514ddd7caddfc3bad353b8e (diff) | |
| download | riscv-openocd-7c3a77c37aebfe52b3e18e4f568399590debbe4a.zip riscv-openocd-7c3a77c37aebfe52b3e18e4f568399590debbe4a.tar.gz riscv-openocd-7c3a77c37aebfe52b3e18e4f568399590debbe4a.tar.bz2 | |
Clarify that RISC-V triggers are optional.
Change-Id: I3a1f5a30385969964351b6ccadf09a3796d34d6b
Signed-off-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | doc/openocd.texi | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index 27543d9..d1aba36 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -10718,8 +10718,9 @@ Perform a 32-bit DMI write of value at address. @subsection RISC-V Trigger Commands -The RISC-V Debug Specification defines several trigger types that don't map -cleanly onto OpenOCD's notion of hardware breakpoints. These commands let you +The RISC-V Debug Specification defines several optional trigger types that don't +map cleanly onto OpenOCD's notion of hardware breakpoints. For the types that +the target supports, these commands let you set those triggers directly. (It's also possible to do so by writing the appropriate CSRs.) |