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| author | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-10 17:39:52 +0300 |
|---|---|---|
| committer | Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> | 2023-01-10 17:41:13 +0300 |
| commit | 71e3d0aecba212768096c30fd2ac7ec20eb72fc0 (patch) | |
| tree | 0f98408171101339e1e845a8291b855e10d51a40 | |
| parent | 43ea20dfbb6c815004a51106a3b2009d7f6c4940 (diff) | |
| download | riscv-openocd-71e3d0aecba212768096c30fd2ac7ec20eb72fc0.zip riscv-openocd-71e3d0aecba212768096c30fd2ac7ec20eb72fc0.tar.gz riscv-openocd-71e3d0aecba212768096c30fd2ac7ec20eb72fc0.tar.bz2 | |
target/riscv: added support for missing VCSR register
Change-Id: I0ce7b9e76c613400916c46fad0f19984ea4b482e
| -rw-r--r-- | src/target/riscv/gdb_regs.h | 1 | ||||
| -rw-r--r-- | src/target/riscv/riscv-013.c | 1 | ||||
| -rw-r--r-- | src/target/riscv/riscv.c | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/src/target/riscv/gdb_regs.h b/src/target/riscv/gdb_regs.h index 43f8b5e..3a46577 100644 --- a/src/target/riscv/gdb_regs.h +++ b/src/target/riscv/gdb_regs.h @@ -81,6 +81,7 @@ enum gdb_regno { GDB_REGNO_VSTART = CSR_VSTART + GDB_REGNO_CSR0, GDB_REGNO_VXSAT = CSR_VXSAT + GDB_REGNO_CSR0, GDB_REGNO_VXRM = CSR_VXRM + GDB_REGNO_CSR0, + GDB_REGNO_VCSR = CSR_VCSR + GDB_REGNO_CSR0, GDB_REGNO_VLENB = CSR_VLENB + GDB_REGNO_CSR0, GDB_REGNO_VL = CSR_VL + GDB_REGNO_CSR0, GDB_REGNO_VTYPE = CSR_VTYPE + GDB_REGNO_CSR0, diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1bf76fc..661197c 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1075,6 +1075,7 @@ static int is_vector_reg(uint32_t gdb_regno) gdb_regno == GDB_REGNO_VSTART || gdb_regno == GDB_REGNO_VXSAT || gdb_regno == GDB_REGNO_VXRM || + gdb_regno == GDB_REGNO_VCSR || gdb_regno == GDB_REGNO_VL || gdb_regno == GDB_REGNO_VTYPE || gdb_regno == GDB_REGNO_VLENB; diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index deeaf43..3787041 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -5188,6 +5188,7 @@ int riscv_init_registers(struct target *target) case CSR_VXSAT: case CSR_VXRM: case CSR_VL: + case CSR_VCSR: case CSR_VTYPE: case CSR_VLENB: r->exist = (info->vlenb > 0); |