diff options
| author | Tim Newsome <tim@sifive.com> | 2023-02-08 11:02:51 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2023-02-08 11:02:51 -0800 |
| commit | 344e8bd26388821512c931edbb8508264d193c04 (patch) | |
| tree | 49d4485a5e0a3a2d156bdcc1df48ba611051ed7a | |
| parent | 91552c79997f9baa859bc9324d5ebea790b1dcba (diff) | |
| download | riscv-openocd-344e8bd26388821512c931edbb8508264d193c04.zip riscv-openocd-344e8bd26388821512c931edbb8508264d193c04.tar.gz riscv-openocd-344e8bd26388821512c931edbb8508264d193c04.tar.bz2 | |
Print out debug value after the assignment is made.
Change-Id: I6ba1064c09f48eba97d84ea9db5ff44d82b9d004
| -rw-r--r-- | src/target/riscv/riscv-013.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 7d3b54d..e2930ab 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1732,8 +1732,8 @@ static int examine(struct target *target) LOG_TARGET_WARNING(target, "Couldn't read vlenb; vector register access won't work."); r->vlenb = 0; } else { - LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb); r->vlenb = vlenb; + LOG_TARGET_INFO(target, "Vector support with vlenb=%d", r->vlenb); } /* Now init registers based on what we discovered. */ |