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| author | Tim Newsome <tim@sifive.com> | 2022-12-27 12:53:52 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2022-12-27 12:54:12 -0800 |
| commit | 2258a59a0f1baa376972818b35530e50645f7c8f (patch) | |
| tree | 3dcbb57bf3c14170e9dbec4a95f969cb238dce05 | |
| parent | eb8bb957d4c34adfe40fb02f57dfafff14e871a8 (diff) | |
| download | riscv-openocd-2258a59a0f1baa376972818b35530e50645f7c8f.zip riscv-openocd-2258a59a0f1baa376972818b35530e50645f7c8f.tar.gz riscv-openocd-2258a59a0f1baa376972818b35530e50645f7c8f.tar.bz2 | |
target/riscv: Use macros for trigger types.
Change-Id: I6ced3fb5a22bff4694fbceb8cf91f6cf6ce37ebf
Signed-off-by: Tim Newsome <tim@sifive.com>
| -rw-r--r-- | src/target/riscv/riscv.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c index 9e46cda..5a59d5a 100644 --- a/src/target/riscv/riscv.c +++ b/src/target/riscv/riscv.c @@ -1071,13 +1071,13 @@ static int riscv_hit_trigger_hit_bit(struct target *target, uint32_t *unique_id) uint64_t hit_mask = 0; switch (type) { - case 1: + case CSR_TDATA1_TYPE_LEGACY: /* Doesn't support hit bit. */ break; - case 2: + case CSR_TDATA1_TYPE_MCONTROL: hit_mask = CSR_MCONTROL_HIT; break; - case 6: + case CSR_TDATA1_TYPE_MCONTROL6: hit_mask = CSR_MCONTROL6_HIT; break; default: @@ -4120,16 +4120,16 @@ int riscv_enumerate_triggers(struct target *target) if (type == 0) break; switch (type) { - case 1: + case CSR_TDATA1_TYPE_LEGACY: /* On these older cores we don't support software using * triggers. */ riscv_set_register(target, GDB_REGNO_TDATA1, 0); break; - case 2: + case CSR_TDATA1_TYPE_MCONTROL: if (tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target))) riscv_set_register(target, GDB_REGNO_TDATA1, 0); break; - case 6: + case CSR_TDATA1_TYPE_MCONTROL6: if (tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target))) riscv_set_register(target, GDB_REGNO_TDATA1, 0); break; |