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| author | Tim Newsome <tim@sifive.com> | 2017-12-11 14:59:11 -0800 |
|---|---|---|
| committer | Tim Newsome <tim@sifive.com> | 2017-12-19 10:41:48 -0800 |
| commit | 10c17fdf17548d5ee32ae23023bb62e532bfef03 (patch) | |
| tree | 1c0b1e3e1a6a9481eebcb3dfa7e8e07ed77a5d09 | |
| parent | ec1c814017af4a4dab865be99dcc31c63d45da36 (diff) | |
| download | riscv-openocd-10c17fdf17548d5ee32ae23023bb62e532bfef03.zip riscv-openocd-10c17fdf17548d5ee32ae23023bb62e532bfef03.tar.gz riscv-openocd-10c17fdf17548d5ee32ae23023bb62e532bfef03.tar.bz2 | |
Read misa before using it to check for extensions.
Change-Id: I7a172d83055d8bd833e3349a5b22b47dd5f31f5c
| -rw-r--r-- | src/target/riscv/riscv-013.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c index 1fff990..6083ba8 100644 --- a/src/target/riscv/riscv-013.c +++ b/src/target/riscv/riscv-013.c @@ -1219,11 +1219,12 @@ static int examine(struct target *target) r->xlen[i] = 32; } + register_read_direct(target, &r->misa, GDB_REGNO_MISA); + // Now init registers based on what we discovered. if (riscv_init_registers(target) != ERROR_OK) return ERROR_FAIL; - r->misa = riscv_get_register_on_hart(target, i, GDB_REGNO_MISA); /* Display this as early as possible to help people who are using * really slow simulators. */ LOG_DEBUG(" hart %d: XLEN=%d, misa=0x%" PRIx64, i, r->xlen[i], |