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authorMegan Wachs <megan@sifive.com>2017-02-07 11:24:12 -0800
committerMegan Wachs <megan@sifive.com>2017-02-07 11:24:12 -0800
commit7b95554ff526a6ac0002373e589d0dafd152900f (patch)
tree61d833009eac3033aabbb8b29f0f9f4adcabf1ee
parent2ae0078fc723d18822ed50f6f3accd32107acbef (diff)
parent075c0e80d1d451e3445fd909e77d23c1c0b654c4 (diff)
downloadriscv-openocd-7b95554ff526a6ac0002373e589d0dafd152900f.zip
riscv-openocd-7b95554ff526a6ac0002373e589d0dafd152900f.tar.gz
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Merge remote-tracking branch 'origin/riscv' into HEAD
Diffstat
-rw-r--r--src/target/Makefile.am2
-rw-r--r--src/target/riscv/debug_defines.h630
-rw-r--r--src/target/riscv/opcodes.h7
-rw-r--r--src/target/riscv/riscv-011.c2601
-rw-r--r--src/target/riscv/riscv-013.c2620
-rw-r--r--src/target/riscv/riscv.c2391
-rw-r--r--src/target/riscv/riscv.h62
7 files changed, 6016 insertions, 2297 deletions
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 40c8ef6..44299fc 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -136,6 +136,8 @@ INTEL_IA32_SRC = \
x86_32_common.c
RISCV_SRC = \
+ riscv/riscv-011.c \
+ riscv/riscv-013.c \
riscv/riscv.c
noinst_HEADERS = \
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
new file mode 100644
index 0000000..3e3653c
--- /dev/null
+++ b/src/target/riscv/debug_defines.h
@@ -0,0 +1,630 @@
+#define ACCESS_REGISTER None
+#define ACCESS_REGISTER_PREHALT_OFFSET 23
+#define ACCESS_REGISTER_PREHALT_LENGTH 1
+#define ACCESS_REGISTER_PREHALT (0x1 << ACCESS_REGISTER_PREHALT_OFFSET)
+#define ACCESS_REGISTER_POSTRESUME_OFFSET 22
+#define ACCESS_REGISTER_POSTRESUME_LENGTH 1
+#define ACCESS_REGISTER_POSTRESUME (0x1 << ACCESS_REGISTER_POSTRESUME_OFFSET)
+#define ACCESS_REGISTER_SIZE_OFFSET 19
+#define ACCESS_REGISTER_SIZE_LENGTH 3
+#define ACCESS_REGISTER_SIZE (0x7 << ACCESS_REGISTER_SIZE_OFFSET)
+#define ACCESS_REGISTER_PREEXEC_OFFSET 18
+#define ACCESS_REGISTER_PREEXEC_LENGTH 1
+#define ACCESS_REGISTER_PREEXEC (0x1 << ACCESS_REGISTER_PREEXEC_OFFSET)
+#define ACCESS_REGISTER_POSTEXEC_OFFSET 17
+#define ACCESS_REGISTER_POSTEXEC_LENGTH 1
+#define ACCESS_REGISTER_POSTEXEC (0x1 << ACCESS_REGISTER_POSTEXEC_OFFSET)
+#define ACCESS_REGISTER_WRITE_OFFSET 16
+#define ACCESS_REGISTER_WRITE_LENGTH 1
+#define ACCESS_REGISTER_WRITE (0x1 << ACCESS_REGISTER_WRITE_OFFSET)
+#define ACCESS_REGISTER_REGNO_OFFSET 0
+#define ACCESS_REGISTER_REGNO_LENGTH 16
+#define ACCESS_REGISTER_REGNO (0xffff << ACCESS_REGISTER_REGNO_OFFSET)
+#define CSR_DCSR 0x7b0
+#define CSR_DCSR_XDEBUGVER_OFFSET 30
+#define CSR_DCSR_XDEBUGVER_LENGTH 2
+#define CSR_DCSR_XDEBUGVER (0x3 << CSR_DCSR_XDEBUGVER_OFFSET)
+#define CSR_DCSR_EBREAKM_OFFSET 15
+#define CSR_DCSR_EBREAKM_LENGTH 1
+#define CSR_DCSR_EBREAKM (0x1 << CSR_DCSR_EBREAKM_OFFSET)
+#define CSR_DCSR_EBREAKH_OFFSET 14
+#define CSR_DCSR_EBREAKH_LENGTH 1
+#define CSR_DCSR_EBREAKH (0x1 << CSR_DCSR_EBREAKH_OFFSET)
+#define CSR_DCSR_EBREAKS_OFFSET 13
+#define CSR_DCSR_EBREAKS_LENGTH 1
+#define CSR_DCSR_EBREAKS (0x1 << CSR_DCSR_EBREAKS_OFFSET)
+#define CSR_DCSR_EBREAKU_OFFSET 12
+#define CSR_DCSR_EBREAKU_LENGTH 1
+#define CSR_DCSR_EBREAKU (0x1 << CSR_DCSR_EBREAKU_OFFSET)
+#define CSR_DCSR_STOPCYCLE_OFFSET 10
+#define CSR_DCSR_STOPCYCLE_LENGTH 1
+#define CSR_DCSR_STOPCYCLE (0x1 << CSR_DCSR_STOPCYCLE_OFFSET)
+#define CSR_DCSR_STOPTIME_OFFSET 9
+#define CSR_DCSR_STOPTIME_LENGTH 1
+#define CSR_DCSR_STOPTIME (0x1 << CSR_DCSR_STOPTIME_OFFSET)
+#define CSR_DCSR_CAUSE_OFFSET 6
+#define CSR_DCSR_CAUSE_LENGTH 3
+#define CSR_DCSR_CAUSE (0x7 << CSR_DCSR_CAUSE_OFFSET)
+#define CSR_DCSR_STEP_OFFSET 2
+#define CSR_DCSR_STEP_LENGTH 1
+#define CSR_DCSR_STEP (0x1 << CSR_DCSR_STEP_OFFSET)
+#define CSR_DCSR_PRV_OFFSET 0
+#define CSR_DCSR_PRV_LENGTH 2
+#define CSR_DCSR_PRV (0x3 << CSR_DCSR_PRV_OFFSET)
+#define CSR_DPC 0x7b1
+#define CSR_DPC_DPC_OFFSET 0
+#define CSR_DPC_DPC_LENGTH XLEN
+#define CSR_DPC_DPC (((1L<<XLEN)-1) << CSR_DPC_DPC_OFFSET)
+#define CSR_DSCRATCH0 0x7b2
+#define CSR_DSCRATCH1 0x7b3
+#define CSR_PRIV virtual
+#define CSR_PRIV_PRV_OFFSET 0
+#define CSR_PRIV_PRV_LENGTH 2
+#define CSR_PRIV_PRV (0x3 << CSR_PRIV_PRV_OFFSET)
+#define DMI_DMCONTROL 0x00
+#define DMI_DMCONTROL_HALT_OFFSET 31
+#define DMI_DMCONTROL_HALT_LENGTH 1
+#define DMI_DMCONTROL_HALT (0x1 << DMI_DMCONTROL_HALT_OFFSET)
+#define DMI_DMCONTROL_RESET_OFFSET 30
+#define DMI_DMCONTROL_RESET_LENGTH 1
+#define DMI_DMCONTROL_RESET (0x1 << DMI_DMCONTROL_RESET_OFFSET)
+#define DMI_DMCONTROL_DMACTIVE_OFFSET 29
+#define DMI_DMCONTROL_DMACTIVE_LENGTH 1
+#define DMI_DMCONTROL_DMACTIVE (0x1 << DMI_DMCONTROL_DMACTIVE_OFFSET)
+#define DMI_DMCONTROL_HARTID_OFFSET 16
+#define DMI_DMCONTROL_HARTID_LENGTH 10
+#define DMI_DMCONTROL_HARTID (0x3ff << DMI_DMCONTROL_HARTID_OFFSET)
+#define DMI_DMCONTROL_AUTHENTICATED_OFFSET 7
+#define DMI_DMCONTROL_AUTHENTICATED_LENGTH 1
+#define DMI_DMCONTROL_AUTHENTICATED (0x1 << DMI_DMCONTROL_AUTHENTICATED_OFFSET)
+#define DMI_DMCONTROL_AUTHBUSY_OFFSET 6
+#define DMI_DMCONTROL_AUTHBUSY_LENGTH 1
+#define DMI_DMCONTROL_AUTHBUSY (0x1 << DMI_DMCONTROL_AUTHBUSY_OFFSET)
+#define DMI_DMCONTROL_AUTHTYPE_OFFSET 4
+#define DMI_DMCONTROL_AUTHTYPE_LENGTH 2
+#define DMI_DMCONTROL_AUTHTYPE (0x3 << DMI_DMCONTROL_AUTHTYPE_OFFSET)
+#define DMI_DMCONTROL_VERSION_OFFSET 0
+#define DMI_DMCONTROL_VERSION_LENGTH 4
+#define DMI_DMCONTROL_VERSION (0xf << DMI_DMCONTROL_VERSION_OFFSET)
+#define DMI_HALTSUM 0x02
+#define DMI_HALTSUM_HALT1023_992_OFFSET 31
+#define DMI_HALTSUM_HALT1023_992_LENGTH 1
+#define DMI_HALTSUM_HALT1023_992 (0x1 << DMI_HALTSUM_HALT1023_992_OFFSET)
+#define DMI_HALTSUM_HALT991_960_OFFSET 30
+#define DMI_HALTSUM_HALT991_960_LENGTH 1
+#define DMI_HALTSUM_HALT991_960 (0x1 << DMI_HALTSUM_HALT991_960_OFFSET)
+#define DMI_HALTSUM_HALT959_928_OFFSET 29
+#define DMI_HALTSUM_HALT959_928_LENGTH 1
+#define DMI_HALTSUM_HALT959_928 (0x1 << DMI_HALTSUM_HALT959_928_OFFSET)
+#define DMI_HALTSUM_HALT927_896_OFFSET 28
+#define DMI_HALTSUM_HALT927_896_LENGTH 1
+#define DMI_HALTSUM_HALT927_896 (0x1 << DMI_HALTSUM_HALT927_896_OFFSET)
+#define DMI_HALTSUM_HALT895_864_OFFSET 27
+#define DMI_HALTSUM_HALT895_864_LENGTH 1
+#define DMI_HALTSUM_HALT895_864 (0x1 << DMI_HALTSUM_HALT895_864_OFFSET)
+#define DMI_HALTSUM_HALT863_832_OFFSET 26
+#define DMI_HALTSUM_HALT863_832_LENGTH 1
+#define DMI_HALTSUM_HALT863_832 (0x1 << DMI_HALTSUM_HALT863_832_OFFSET)
+#define DMI_HALTSUM_HALT831_800_OFFSET 25
+#define DMI_HALTSUM_HALT831_800_LENGTH 1
+#define DMI_HALTSUM_HALT831_800 (0x1 << DMI_HALTSUM_HALT831_800_OFFSET)
+#define DMI_HALTSUM_HALT799_768_OFFSET 24
+#define DMI_HALTSUM_HALT799_768_LENGTH 1
+#define DMI_HALTSUM_HALT799_768 (0x1 << DMI_HALTSUM_HALT799_768_OFFSET)
+#define DMI_HALTSUM_HALT767_736_OFFSET 23
+#define DMI_HALTSUM_HALT767_736_LENGTH 1
+#define DMI_HALTSUM_HALT767_736 (0x1 << DMI_HALTSUM_HALT767_736_OFFSET)
+#define DMI_HALTSUM_HALT735_704_OFFSET 22
+#define DMI_HALTSUM_HALT735_704_LENGTH 1
+#define DMI_HALTSUM_HALT735_704 (0x1 << DMI_HALTSUM_HALT735_704_OFFSET)
+#define DMI_HALTSUM_HALT703_672_OFFSET 21
+#define DMI_HALTSUM_HALT703_672_LENGTH 1
+#define DMI_HALTSUM_HALT703_672 (0x1 << DMI_HALTSUM_HALT703_672_OFFSET)
+#define DMI_HALTSUM_HALT671_640_OFFSET 20
+#define DMI_HALTSUM_HALT671_640_LENGTH 1
+#define DMI_HALTSUM_HALT671_640 (0x1 << DMI_HALTSUM_HALT671_640_OFFSET)
+#define DMI_HALTSUM_HALT639_608_OFFSET 19
+#define DMI_HALTSUM_HALT639_608_LENGTH 1
+#define DMI_HALTSUM_HALT639_608 (0x1 << DMI_HALTSUM_HALT639_608_OFFSET)
+#define DMI_HALTSUM_HALT607_576_OFFSET 18
+#define DMI_HALTSUM_HALT607_576_LENGTH 1
+#define DMI_HALTSUM_HALT607_576 (0x1 << DMI_HALTSUM_HALT607_576_OFFSET)
+#define DMI_HALTSUM_HALT575_544_OFFSET 17
+#define DMI_HALTSUM_HALT575_544_LENGTH 1
+#define DMI_HALTSUM_HALT575_544 (0x1 << DMI_HALTSUM_HALT575_544_OFFSET)
+#define DMI_HALTSUM_HALT543_512_OFFSET 16
+#define DMI_HALTSUM_HALT543_512_LENGTH 1
+#define DMI_HALTSUM_HALT543_512 (0x1 << DMI_HALTSUM_HALT543_512_OFFSET)
+#define DMI_HALTSUM_HALT511_480_OFFSET 15
+#define DMI_HALTSUM_HALT511_480_LENGTH 1
+#define DMI_HALTSUM_HALT511_480 (0x1 << DMI_HALTSUM_HALT511_480_OFFSET)
+#define DMI_HALTSUM_HALT479_448_OFFSET 14
+#define DMI_HALTSUM_HALT479_448_LENGTH 1
+#define DMI_HALTSUM_HALT479_448 (0x1 << DMI_HALTSUM_HALT479_448_OFFSET)
+#define DMI_HALTSUM_HALT447_416_OFFSET 13
+#define DMI_HALTSUM_HALT447_416_LENGTH 1
+#define DMI_HALTSUM_HALT447_416 (0x1 << DMI_HALTSUM_HALT447_416_OFFSET)
+#define DMI_HALTSUM_HALT415_384_OFFSET 12
+#define DMI_HALTSUM_HALT415_384_LENGTH 1
+#define DMI_HALTSUM_HALT415_384 (0x1 << DMI_HALTSUM_HALT415_384_OFFSET)
+#define DMI_HALTSUM_HALT383_352_OFFSET 11
+#define DMI_HALTSUM_HALT383_352_LENGTH 1
+#define DMI_HALTSUM_HALT383_352 (0x1 << DMI_HALTSUM_HALT383_352_OFFSET)
+#define DMI_HALTSUM_HALT351_320_OFFSET 10
+#define DMI_HALTSUM_HALT351_320_LENGTH 1
+#define DMI_HALTSUM_HALT351_320 (0x1 << DMI_HALTSUM_HALT351_320_OFFSET)
+#define DMI_HALTSUM_HALT319_288_OFFSET 9
+#define DMI_HALTSUM_HALT319_288_LENGTH 1
+#define DMI_HALTSUM_HALT319_288 (0x1 << DMI_HALTSUM_HALT319_288_OFFSET)
+#define DMI_HALTSUM_HALT287_256_OFFSET 8
+#define DMI_HALTSUM_HALT287_256_LENGTH 1
+#define DMI_HALTSUM_HALT287_256 (0x1 << DMI_HALTSUM_HALT287_256_OFFSET)
+#define DMI_HALTSUM_HALT255_224_OFFSET 7
+#define DMI_HALTSUM_HALT255_224_LENGTH 1
+#define DMI_HALTSUM_HALT255_224 (0x1 << DMI_HALTSUM_HALT255_224_OFFSET)
+#define DMI_HALTSUM_HALT223_192_OFFSET 6
+#define DMI_HALTSUM_HALT223_192_LENGTH 1
+#define DMI_HALTSUM_HALT223_192 (0x1 << DMI_HALTSUM_HALT223_192_OFFSET)
+#define DMI_HALTSUM_HALT191_160_OFFSET 5
+#define DMI_HALTSUM_HALT191_160_LENGTH 1
+#define DMI_HALTSUM_HALT191_160 (0x1 << DMI_HALTSUM_HALT191_160_OFFSET)
+#define DMI_HALTSUM_HALT159_128_OFFSET 4
+#define DMI_HALTSUM_HALT159_128_LENGTH 1
+#define DMI_HALTSUM_HALT159_128 (0x1 << DMI_HALTSUM_HALT159_128_OFFSET)
+#define DMI_HALTSUM_HALT127_96_OFFSET 3
+#define DMI_HALTSUM_HALT127_96_LENGTH 1
+#define DMI_HALTSUM_HALT127_96 (0x1 << DMI_HALTSUM_HALT127_96_OFFSET)
+#define DMI_HALTSUM_HALT95_64_OFFSET 2
+#define DMI_HALTSUM_HALT95_64_LENGTH 1
+#define DMI_HALTSUM_HALT95_64 (0x1 << DMI_HALTSUM_HALT95_64_OFFSET)
+#define DMI_HALTSUM_HALT63_32_OFFSET 1
+#define DMI_HALTSUM_HALT63_32_LENGTH 1
+#define DMI_HALTSUM_HALT63_32 (0x1 << DMI_HALTSUM_HALT63_32_OFFSET)
+#define DMI_HALTSUM_HALT31_0_OFFSET 0
+#define DMI_HALTSUM_HALT31_0_LENGTH 1
+#define DMI_HALTSUM_HALT31_0 (0x1 << DMI_HALTSUM_HALT31_0_OFFSET)
+#define DMI_SBCS 0x03
+#define DMI_SBCS_SBSINGLEREAD_OFFSET 20
+#define DMI_SBCS_SBSINGLEREAD_LENGTH 1
+#define DMI_SBCS_SBSINGLEREAD (0x1 << DMI_SBCS_SBSINGLEREAD_OFFSET)
+#define DMI_SBCS_SBACCESS_OFFSET 17
+#define DMI_SBCS_SBACCESS_LENGTH 3
+#define DMI_SBCS_SBACCESS (0x7 << DMI_SBCS_SBACCESS_OFFSET)
+#define DMI_SBCS_SBAUTOINCREMENT_OFFSET 16
+#define DMI_SBCS_SBAUTOINCREMENT_LENGTH 1
+#define DMI_SBCS_SBAUTOINCREMENT (0x1 << DMI_SBCS_SBAUTOINCREMENT_OFFSET)
+#define DMI_SBCS_SBAUTOREAD_OFFSET 15
+#define DMI_SBCS_SBAUTOREAD_LENGTH 1
+#define DMI_SBCS_SBAUTOREAD (0x1 << DMI_SBCS_SBAUTOREAD_OFFSET)
+#define DMI_SBCS_SBERROR_OFFSET 12
+#define DMI_SBCS_SBERROR_LENGTH 3
+#define DMI_SBCS_SBERROR (0x7 << DMI_SBCS_SBERROR_OFFSET)
+#define DMI_SBCS_SBASIZE_OFFSET 5
+#define DMI_SBCS_SBASIZE_LENGTH 7
+#define DMI_SBCS_SBASIZE (0x7f << DMI_SBCS_SBASIZE_OFFSET)
+#define DMI_SBCS_SBACCESS128_OFFSET 4
+#define DMI_SBCS_SBACCESS128_LENGTH 1
+#define DMI_SBCS_SBACCESS128 (0x1 << DMI_SBCS_SBACCESS128_OFFSET)
+#define DMI_SBCS_SBACCESS64_OFFSET 3
+#define DMI_SBCS_SBACCESS64_LENGTH 1
+#define DMI_SBCS_SBACCESS64 (0x1 << DMI_SBCS_SBACCESS64_OFFSET)
+#define DMI_SBCS_SBACCESS32_OFFSET 2
+#define DMI_SBCS_SBACCESS32_LENGTH 1
+#define DMI_SBCS_SBACCESS32 (0x1 << DMI_SBCS_SBACCESS32_OFFSET)
+#define DMI_SBCS_SBACCESS16_OFFSET 1
+#define DMI_SBCS_SBACCESS16_LENGTH 1
+#define DMI_SBCS_SBACCESS16 (0x1 << DMI_SBCS_SBACCESS16_OFFSET)
+#define DMI_SBCS_SBACCESS8_OFFSET 0
+#define DMI_SBCS_SBACCESS8_LENGTH 1
+#define DMI_SBCS_SBACCESS8 (0x1 << DMI_SBCS_SBACCESS8_OFFSET)
+#define DMI_SBADDRESS0 0x04
+#define DMI_SBADDRESS0_ADDRESS_OFFSET 0
+#define DMI_SBADDRESS0_ADDRESS_LENGTH 32
+#define DMI_SBADDRESS0_ADDRESS (0xffffffff << DMI_SBADDRESS0_ADDRESS_OFFSET)
+#define DMI_SBADDRESS1 0x05
+#define DMI_SBADDRESS1_ADDRESS_OFFSET 0
+#define DMI_SBADDRESS1_ADDRESS_LENGTH 32
+#define DMI_SBADDRESS1_ADDRESS (0xffffffff << DMI_SBADDRESS1_ADDRESS_OFFSET)
+#define DMI_SBADDRESS2 0x06
+#define DMI_SBADDRESS2_BUSY_OFFSET 31
+#define DMI_SBADDRESS2_BUSY_LENGTH 1
+#define DMI_SBADDRESS2_BUSY (0x1 << DMI_SBADDRESS2_BUSY_OFFSET)
+#define DMI_SBADDRESS2_ADDRESS_OFFSET 0
+#define DMI_SBADDRESS2_ADDRESS_LENGTH 31
+#define DMI_SBADDRESS2_ADDRESS (0x7fffffff << DMI_SBADDRESS2_ADDRESS_OFFSET)
+#define DMI_SBDATA0 0x07
+#define DMI_SBDATA0_DATA_OFFSET 0
+#define DMI_SBDATA0_DATA_LENGTH 32
+#define DMI_SBDATA0_DATA (0xffffffff << DMI_SBDATA0_DATA_OFFSET)
+#define DMI_SBDATA1 0x08
+#define DMI_SBDATA1_DATA_OFFSET 0
+#define DMI_SBDATA1_DATA_LENGTH 32
+#define DMI_SBDATA1_DATA (0xffffffff << DMI_SBDATA1_DATA_OFFSET)
+#define DMI_SBDATA2 0x09
+#define DMI_SBDATA2_DATA_OFFSET 0
+#define DMI_SBDATA2_DATA_LENGTH 32
+#define DMI_SBDATA2_DATA (0xffffffff << DMI_SBDATA2_DATA_OFFSET)
+#define DMI_SBDATA3 0x0a
+#define DMI_SBDATA3_DATA_OFFSET 0
+#define DMI_SBDATA3_DATA_LENGTH 32
+#define DMI_SBDATA3_DATA (0xffffffff << DMI_SBDATA3_DATA_OFFSET)
+#define DMI_ABSTRACTCS 0x0b
+#define DMI_ABSTRACTCS_AUTOEXEC7_OFFSET 15
+#define DMI_ABSTRACTCS_AUTOEXEC7_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC7 (0x1 << DMI_ABSTRACTCS_AUTOEXEC7_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC6_OFFSET 14
+#define DMI_ABSTRACTCS_AUTOEXEC6_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC6 (0x1 << DMI_ABSTRACTCS_AUTOEXEC6_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC5_OFFSET 13
+#define DMI_ABSTRACTCS_AUTOEXEC5_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC5 (0x1 << DMI_ABSTRACTCS_AUTOEXEC5_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC4_OFFSET 12
+#define DMI_ABSTRACTCS_AUTOEXEC4_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC4 (0x1 << DMI_ABSTRACTCS_AUTOEXEC4_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC3_OFFSET 11
+#define DMI_ABSTRACTCS_AUTOEXEC3_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC3 (0x1 << DMI_ABSTRACTCS_AUTOEXEC3_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC2_OFFSET 10
+#define DMI_ABSTRACTCS_AUTOEXEC2_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC2 (0x1 << DMI_ABSTRACTCS_AUTOEXEC2_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC1_OFFSET 9
+#define DMI_ABSTRACTCS_AUTOEXEC1_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC1 (0x1 << DMI_ABSTRACTCS_AUTOEXEC1_OFFSET)
+#define DMI_ABSTRACTCS_AUTOEXEC0_OFFSET 8
+#define DMI_ABSTRACTCS_AUTOEXEC0_LENGTH 1
+#define DMI_ABSTRACTCS_AUTOEXEC0 (0x1 << DMI_ABSTRACTCS_AUTOEXEC0_OFFSET)
+#define DMI_ABSTRACTCS_CMDERR_OFFSET 5
+#define DMI_ABSTRACTCS_CMDERR_LENGTH 3
+#define DMI_ABSTRACTCS_CMDERR (0x7 << DMI_ABSTRACTCS_CMDERR_OFFSET)
+#define DMI_ABSTRACTCS_BUSY_OFFSET 4
+#define DMI_ABSTRACTCS_BUSY_LENGTH 1
+#define DMI_ABSTRACTCS_BUSY (0x1 << DMI_ABSTRACTCS_BUSY_OFFSET)
+#define DMI_ABSTRACTCS_DATACOUNT_OFFSET 0
+#define DMI_ABSTRACTCS_DATACOUNT_LENGTH 4
+#define DMI_ABSTRACTCS_DATACOUNT (0xf << DMI_ABSTRACTCS_DATACOUNT_OFFSET)
+#define DMI_COMMAND 0x0c
+#define DMI_COMMAND_COMMAND_OFFSET 0
+#define DMI_COMMAND_COMMAND_LENGTH 32
+#define DMI_COMMAND_COMMAND (0xffffffff << DMI_COMMAND_COMMAND_OFFSET)
+#define DMI_DATA0 0x0d
+#define DMI_DATA0_DATA_OFFSET 0
+#define DMI_DATA0_DATA_LENGTH 32
+#define DMI_DATA0_DATA (0xffffffff << DMI_DATA0_DATA_OFFSET)
+#define DMI_DATA1 0x0e
+#define DMI_DATA2 0x0f
+#define DMI_DATA3 0x10
+#define DMI_DATA4 0x11
+#define DMI_DATA5 0x12
+#define DMI_DATA6 0x13
+#define DMI_DATA7 0x14
+#define DMI_ACCESSCS 0x15
+#define DMI_ACCESSCS_PROGSIZE_OFFSET 0
+#define DMI_ACCESSCS_PROGSIZE_LENGTH 4
+#define DMI_ACCESSCS_PROGSIZE (0xf << DMI_ACCESSCS_PROGSIZE_OFFSET)
+#define DMI_IBUF0 0x18
+#define DMI_IBUF0_DATA_OFFSET 0
+#define DMI_IBUF0_DATA_LENGTH 32
+#define DMI_IBUF0_DATA (0xffffffff << DMI_IBUF0_DATA_OFFSET)
+#define DMI_IBUF1 0x19
+#define DMI_IBUF2 0x1a
+#define DMI_IBUF3 0x1b
+#define DMI_IBUF4 0x1c
+#define DMI_IBUF5 0x1d
+#define DMI_IBUF6 0x1e
+#define DMI_IBUF7 0x1f
+#define DMI_AUTHDATA0 0x20
+#define DMI_AUTHDATA0_DATA_OFFSET 0
+#define DMI_AUTHDATA0_DATA_LENGTH 32
+#define DMI_AUTHDATA0_DATA (0xffffffff << DMI_AUTHDATA0_DATA_OFFSET)
+#define DMI_AUTHDATA1 0x21
+#define DMI_AUTHDATA1_DATA_OFFSET 0
+#define DMI_AUTHDATA1_DATA_LENGTH 32
+#define DMI_AUTHDATA1_DATA (0xffffffff << DMI_AUTHDATA1_DATA_OFFSET)
+#define DMI_SERDATA 0x22
+#define DMI_SERDATA_DATA_OFFSET 0
+#define DMI_SERDATA_DATA_LENGTH 32
+#define DMI_SERDATA_DATA (0xffffffff << DMI_SERDATA_DATA_OFFSET)
+#define DMI_SERSTATUS 0x23
+#define DMI_SERSTATUS_SERIALCOUNT_OFFSET 28
+#define DMI_SERSTATUS_SERIALCOUNT_LENGTH 4
+#define DMI_SERSTATUS_SERIALCOUNT (0xf << DMI_SERSTATUS_SERIALCOUNT_OFFSET)
+#define DMI_SERSTATUS_SERIAL_OFFSET 16
+#define DMI_SERSTATUS_SERIAL_LENGTH 3
+#define DMI_SERSTATUS_SERIAL (0x7 << DMI_SERSTATUS_SERIAL_OFFSET)
+#define DMI_SERSTATUS_VALID7_OFFSET 15
+#define DMI_SERSTATUS_VALID7_LENGTH 1
+#define DMI_SERSTATUS_VALID7 (0x1 << DMI_SERSTATUS_VALID7_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW7_OFFSET 14
+#define DMI_SERSTATUS_FULL_OVERFLOW7_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW7 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW7_OFFSET)
+#define DMI_SERSTATUS_VALID6_OFFSET 13
+#define DMI_SERSTATUS_VALID6_LENGTH 1
+#define DMI_SERSTATUS_VALID6 (0x1 << DMI_SERSTATUS_VALID6_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW6_OFFSET 12
+#define DMI_SERSTATUS_FULL_OVERFLOW6_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW6 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW6_OFFSET)
+#define DMI_SERSTATUS_VALID5_OFFSET 11
+#define DMI_SERSTATUS_VALID5_LENGTH 1
+#define DMI_SERSTATUS_VALID5 (0x1 << DMI_SERSTATUS_VALID5_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW5_OFFSET 10
+#define DMI_SERSTATUS_FULL_OVERFLOW5_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW5 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW5_OFFSET)
+#define DMI_SERSTATUS_VALID4_OFFSET 9
+#define DMI_SERSTATUS_VALID4_LENGTH 1
+#define DMI_SERSTATUS_VALID4 (0x1 << DMI_SERSTATUS_VALID4_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW4_OFFSET 8
+#define DMI_SERSTATUS_FULL_OVERFLOW4_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW4 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW4_OFFSET)
+#define DMI_SERSTATUS_VALID3_OFFSET 7
+#define DMI_SERSTATUS_VALID3_LENGTH 1
+#define DMI_SERSTATUS_VALID3 (0x1 << DMI_SERSTATUS_VALID3_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW3_OFFSET 6
+#define DMI_SERSTATUS_FULL_OVERFLOW3_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW3 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW3_OFFSET)
+#define DMI_SERSTATUS_VALID2_OFFSET 5
+#define DMI_SERSTATUS_VALID2_LENGTH 1
+#define DMI_SERSTATUS_VALID2 (0x1 << DMI_SERSTATUS_VALID2_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW2_OFFSET 4
+#define DMI_SERSTATUS_FULL_OVERFLOW2_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW2 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW2_OFFSET)
+#define DMI_SERSTATUS_VALID1_OFFSET 3
+#define DMI_SERSTATUS_VALID1_LENGTH 1
+#define DMI_SERSTATUS_VALID1 (0x1 << DMI_SERSTATUS_VALID1_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW1_OFFSET 2
+#define DMI_SERSTATUS_FULL_OVERFLOW1_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW1 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW1_OFFSET)
+#define DMI_SERSTATUS_VALID0_OFFSET 1
+#define DMI_SERSTATUS_VALID0_LENGTH 1
+#define DMI_SERSTATUS_VALID0 (0x1 << DMI_SERSTATUS_VALID0_OFFSET)
+#define DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET 0
+#define DMI_SERSTATUS_FULL_OVERFLOW0_LENGTH 1
+#define DMI_SERSTATUS_FULL_OVERFLOW0 (0x1 << DMI_SERSTATUS_FULL_OVERFLOW0_OFFSET)
+#define SERINFO 0x110
+#define SERINFO_SERIAL7_OFFSET 7
+#define SERINFO_SERIAL7_LENGTH 1
+#define SERINFO_SERIAL7 (0x1 << SERINFO_SERIAL7_OFFSET)
+#define SERINFO_SERIAL6_OFFSET 6
+#define SERINFO_SERIAL6_LENGTH 1
+#define SERINFO_SERIAL6 (0x1 << SERINFO_SERIAL6_OFFSET)
+#define SERINFO_SERIAL5_OFFSET 5
+#define SERINFO_SERIAL5_LENGTH 1
+#define SERINFO_SERIAL5 (0x1 << SERINFO_SERIAL5_OFFSET)
+#define SERINFO_SERIAL4_OFFSET 4
+#define SERINFO_SERIAL4_LENGTH 1
+#define SERINFO_SERIAL4 (0x1 << SERINFO_SERIAL4_OFFSET)
+#define SERINFO_SERIAL3_OFFSET 3
+#define SERINFO_SERIAL3_LENGTH 1
+#define SERINFO_SERIAL3 (0x1 << SERINFO_SERIAL3_OFFSET)
+#define SERINFO_SERIAL2_OFFSET 2
+#define SERINFO_SERIAL2_LENGTH 1
+#define SERINFO_SERIAL2 (0x1 << SERINFO_SERIAL2_OFFSET)
+#define SERINFO_SERIAL1_OFFSET 1
+#define SERINFO_SERIAL1_LENGTH 1
+#define SERINFO_SERIAL1 (0x1 << SERINFO_SERIAL1_OFFSET)
+#define SERINFO_SERIAL0_OFFSET 0
+#define SERINFO_SERIAL0_LENGTH 1
+#define SERINFO_SERIAL0 (0x1 << SERINFO_SERIAL0_OFFSET)
+#define SERSEND0 0x200
+#define SERRECV0 0x204
+#define SERSTAT0 0x208
+#define SERSTAT0_SENDR_OFFSET 1
+#define SERSTAT0_SENDR_LENGTH 1
+#define SERSTAT0_SENDR (0x1 << SERSTAT0_SENDR_OFFSET)
+#define SERSTAT0_RECVR_OFFSET 0
+#define SERSTAT0_RECVR_LENGTH 1
+#define SERSTAT0_RECVR (0x1 << SERSTAT0_RECVR_OFFSET)
+#define SERSEND1 0x20c
+#define SERRECV1 0x210
+#define SERSTAT1 0x214
+#define SERSEND2 0x218
+#define SERRECV2 0x21c
+#define SERSTAT2 0x220
+#define SERSEND3 0x224
+#define SERRECV3 0x228
+#define SERSTAT3 0x22c
+#define SERSEND4 0x230
+#define SERRECV4 0x234
+#define SERSTAT4 0x238
+#define SERSEND5 0x23c
+#define SERRECV5 0x240
+#define SERSTAT5 0x244
+#define SERSEND6 0x248
+#define SERRECV6 0x24c
+#define SERSTAT6 0x250
+#define SERSEND7 0x254
+#define SERRECV7 0x258
+#define SERSTAT7 0x25c
+#define CSR_TSELECT 0x7a0
+#define CSR_TSELECT_INDEX_OFFSET 0
+#define CSR_TSELECT_INDEX_LENGTH XLEN
+#define CSR_TSELECT_INDEX (((1L<<XLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA1_TYPE_OFFSET XLEN-4
+#define CSR_TDATA1_TYPE_LENGTH 4
+#define CSR_TDATA1_TYPE (0xf << CSR_TDATA1_TYPE_OFFSET)
+#define CSR_TDATA1_DMODE_OFFSET XLEN-5
+#define CSR_TDATA1_DMODE_LENGTH 1
+#define CSR_TDATA1_DMODE (0x1 << CSR_TDATA1_DMODE_OFFSET)
+#define CSR_TDATA1_DATA_OFFSET 0
+#define CSR_TDATA1_DATA_LENGTH XLEN - 5
+#define CSR_TDATA1_DATA (((1L<<XLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA2_DATA_OFFSET 0
+#define CSR_TDATA2_DATA_LENGTH XLEN
+#define CSR_TDATA2_DATA (((1L<<XLEN)-1) << CSR_TDATA2_DATA_OFFSET)
+#define CSR_TDATA3 0x7a3
+#define CSR_TDATA3_DATA_OFFSET 0
+#define CSR_TDATA3_DATA_LENGTH XLEN
+#define CSR_TDATA3_DATA (((1L<<XLEN)-1) << CSR_TDATA3_DATA_OFFSET)
+#define CSR_MCONTROL 0x7a1
+#define CSR_MCONTROL_TYPE_OFFSET XLEN-4
+#define CSR_MCONTROL_TYPE_LENGTH 4
+#define CSR_MCONTROL_TYPE (0xf << CSR_MCONTROL_TYPE_OFFSET)
+#define CSR_MCONTROL_DMODE_OFFSET XLEN-5
+#define CSR_MCONTROL_DMODE_LENGTH 1
+#define CSR_MCONTROL_DMODE (0x1 << CSR_MCONTROL_DMODE_OFFSET)
+#define CSR_MCONTROL_MASKMAX_OFFSET XLEN-11
+#define CSR_MCONTROL_MASKMAX_LENGTH 6
+#define CSR_MCONTROL_MASKMAX (0x3f << CSR_MCONTROL_MASKMAX_OFFSET)
+#define CSR_MCONTROL_SELECT_OFFSET 19
+#define CSR_MCONTROL_SELECT_LENGTH 1
+#define CSR_MCONTROL_SELECT (0x1 << CSR_MCONTROL_SELECT_OFFSET)
+#define CSR_MCONTROL_TIMING_OFFSET 18
+#define CSR_MCONTROL_TIMING_LENGTH 1
+#define CSR_MCONTROL_TIMING (0x1 << CSR_MCONTROL_TIMING_OFFSET)
+#define CSR_MCONTROL_ACTION_OFFSET 12
+#define CSR_MCONTROL_ACTION_LENGTH 6
+#define CSR_MCONTROL_ACTION (0x3f << CSR_MCONTROL_ACTION_OFFSET)
+#define CSR_MCONTROL_CHAIN_OFFSET 11
+#define CSR_MCONTROL_CHAIN_LENGTH 1
+#define CSR_MCONTROL_CHAIN (0x1 << CSR_MCONTROL_CHAIN_OFFSET)
+#define CSR_MCONTROL_MATCH_OFFSET 7
+#define CSR_MCONTROL_MATCH_LENGTH 4
+#define CSR_MCONTROL_MATCH (0xf << CSR_MCONTROL_MATCH_OFFSET)
+#define CSR_MCONTROL_M_OFFSET 6
+#define CSR_MCONTROL_M_LENGTH 1
+#define CSR_MCONTROL_M (0x1 << CSR_MCONTROL_M_OFFSET)
+#define CSR_MCONTROL_H_OFFSET 5
+#define CSR_MCONTROL_H_LENGTH 1
+#define CSR_MCONTROL_H (0x1 << CSR_MCONTROL_H_OFFSET)
+#define CSR_MCONTROL_S_OFFSET 4
+#define CSR_MCONTROL_S_LENGTH 1
+#define CSR_MCONTROL_S (0x1 << CSR_MCONTROL_S_OFFSET)
+#define CSR_MCONTROL_U_OFFSET 3
+#define CSR_MCONTROL_U_LENGTH 1
+#define CSR_MCONTROL_U (0x1 << CSR_MCONTROL_U_OFFSET)
+#define CSR_MCONTROL_EXECUTE_OFFSET 2
+#define CSR_MCONTROL_EXECUTE_LENGTH 1
+#define CSR_MCONTROL_EXECUTE (0x1 << CSR_MCONTROL_EXECUTE_OFFSET)
+#define CSR_MCONTROL_STORE_OFFSET 1
+#define CSR_MCONTROL_STORE_LENGTH 1
+#define CSR_MCONTROL_STORE (0x1 << CSR_MCONTROL_STORE_OFFSET)
+#define CSR_MCONTROL_LOAD_OFFSET 0
+#define CSR_MCONTROL_LOAD_LENGTH 1
+#define CSR_MCONTROL_LOAD (0x1 << CSR_MCONTROL_LOAD_OFFSET)
+#define CSR_ICOUNT 0x7a1
+#define CSR_ICOUNT_TYPE_OFFSET XLEN-4
+#define CSR_ICOUNT_TYPE_LENGTH 4
+#define CSR_ICOUNT_TYPE (0xf << CSR_ICOUNT_TYPE_OFFSET)
+#define CSR_ICOUNT_DMODE_OFFSET XLEN-5
+#define CSR_ICOUNT_DMODE_LENGTH 1
+#define CSR_ICOUNT_DMODE (0x1 << CSR_ICOUNT_DMODE_OFFSET)
+#define CSR_ICOUNT_COUNT_OFFSET 10
+#define CSR_ICOUNT_COUNT_LENGTH 14
+#define CSR_ICOUNT_COUNT (0x3fff << CSR_ICOUNT_COUNT_OFFSET)
+#define CSR_ICOUNT_M_OFFSET 9
+#define CSR_ICOUNT_M_LENGTH 1
+#define CSR_ICOUNT_M (0x1 << CSR_ICOUNT_M_OFFSET)
+#define CSR_ICOUNT_H_OFFSET 8
+#define CSR_ICOUNT_H_LENGTH 1
+#define CSR_ICOUNT_H (0x1 << CSR_ICOUNT_H_OFFSET)
+#define CSR_ICOUNT_S_OFFSET 7
+#define CSR_ICOUNT_S_LENGTH 1
+#define CSR_ICOUNT_S (0x1 << CSR_ICOUNT_S_OFFSET)
+#define CSR_ICOUNT_U_OFFSET 6
+#define CSR_ICOUNT_U_LENGTH 1
+#define CSR_ICOUNT_U (0x1 << CSR_ICOUNT_U_OFFSET)
+#define CSR_ICOUNT_ACTION_OFFSET 0
+#define CSR_ICOUNT_ACTION_LENGTH 6
+#define CSR_ICOUNT_ACTION (0x3f << CSR_ICOUNT_ACTION_OFFSET)
+#define DTM_IDCODE 0x01
+#define DTM_IDCODE_VERSION_OFFSET 28
+#define DTM_IDCODE_VERSION_LENGTH 4
+#define DTM_IDCODE_VERSION (0xf << DTM_IDCODE_VERSION_OFFSET)
+#define DTM_IDCODE_PARTNUMBER_OFFSET 12
+#define DTM_IDCODE_PARTNUMBER_LENGTH 16
+#define DTM_IDCODE_PARTNUMBER (0xffff << DTM_IDCODE_PARTNUMBER_OFFSET)
+#define DTM_IDCODE_MANUFID_OFFSET 1
+#define DTM_IDCODE_MANUFID_LENGTH 11
+#define DTM_IDCODE_MANUFID (0x7ff << DTM_IDCODE_MANUFID_OFFSET)
+#define DTM_IDCODE_1_OFFSET 0
+#define DTM_IDCODE_1_LENGTH 1
+#define DTM_IDCODE_1 (0x1 << DTM_IDCODE_1_OFFSET)
+#define DTM_SAMPLE 0x02
+#define DTM_PRELOAD 0x03
+#define DTM_EXTEST 0x04
+#define DTM_CLAMP 0x05
+#define DTM_CLAMP__HOLD 0x06
+#define DTM_CLAMP__RELEASE 0x07
+#define DTM_HIGHZ 0x08
+#define DTM_IC__RESET 0x09
+#define DTM_TMP__STATUS 0x0a
+#define DTM_INIT__SETUP 0x0b
+#define DTM_INIT__SETUP__CLAMP 0x0c
+#define DTM_INIT__RUN 0x0d
+#define DTM_DTMCONTROL 0x10
+#define DTM_DTMCONTROL_DBUSRESET_OFFSET 16
+#define DTM_DTMCONTROL_DBUSRESET_LENGTH 1
+#define DTM_DTMCONTROL_DBUSRESET (0x1 << DTM_DTMCONTROL_DBUSRESET_OFFSET)
+#define DTM_DTMCONTROL_IDLE_OFFSET 12
+#define DTM_DTMCONTROL_IDLE_LENGTH 3
+#define DTM_DTMCONTROL_IDLE (0x7 << DTM_DTMCONTROL_IDLE_OFFSET)
+#define DTM_DTMCONTROL_DBUSSTAT_OFFSET 10
+#define DTM_DTMCONTROL_DBUSSTAT_LENGTH 2
+#define DTM_DTMCONTROL_DBUSSTAT (0x3 << DTM_DTMCONTROL_DBUSSTAT_OFFSET)
+#define DTM_DTMCONTROL_ABITS_OFFSET 4
+#define DTM_DTMCONTROL_ABITS_LENGTH 6
+#define DTM_DTMCONTROL_ABITS (0x3f << DTM_DTMCONTROL_ABITS_OFFSET)
+#define DTM_DTMCONTROL_VERSION_OFFSET 0
+#define DTM_DTMCONTROL_VERSION_LENGTH 4
+#define DTM_DTMCONTROL_VERSION (0xf << DTM_DTMCONTROL_VERSION_OFFSET)
+#define DTM_DBUS 0x11
+#define DTM_DBUS_ADDRESS_OFFSET 34
+#define DTM_DBUS_ADDRESS_LENGTH abits
+#define DTM_DBUS_ADDRESS (((1L<<abits)-1) << DTM_DBUS_ADDRESS_OFFSET)
+#define DTM_DBUS_DATA_OFFSET 2
+#define DTM_DBUS_DATA_LENGTH 32
+#define DTM_DBUS_DATA (0xffffffff << DTM_DBUS_DATA_OFFSET)
+#define DTM_DBUS_OP_OFFSET 0
+#define DTM_DBUS_OP_LENGTH 2
+#define DTM_DBUS_OP (0x3 << DTM_DBUS_OP_OFFSET)
+#define SHORTNAME 0x123
+#define SHORTNAME_FIELD_OFFSET 0
+#define SHORTNAME_FIELD_LENGTH 8
+#define SHORTNAME_FIELD (0xff << SHORTNAME_FIELD_OFFSET)
+#define TRACE 0x728
+#define TRACE_WRAPPED_OFFSET 24
+#define TRACE_WRAPPED_LENGTH 1
+#define TRACE_WRAPPED (0x1 << TRACE_WRAPPED_OFFSET)
+#define TRACE_EMITTIMESTAMP_OFFSET 23
+#define TRACE_EMITTIMESTAMP_LENGTH 1
+#define TRACE_EMITTIMESTAMP (0x1 << TRACE_EMITTIMESTAMP_OFFSET)
+#define TRACE_EMITSTOREDATA_OFFSET 22
+#define TRACE_EMITSTOREDATA_LENGTH 1
+#define TRACE_EMITSTOREDATA (0x1 << TRACE_EMITSTOREDATA_OFFSET)
+#define TRACE_EMITLOADDATA_OFFSET 21
+#define TRACE_EMITLOADDATA_LENGTH 1
+#define TRACE_EMITLOADDATA (0x1 << TRACE_EMITLOADDATA_OFFSET)
+#define TRACE_EMITSTOREADDR_OFFSET 20
+#define TRACE_EMITSTOREADDR_LENGTH 1
+#define TRACE_EMITSTOREADDR (0x1 << TRACE_EMITSTOREADDR_OFFSET)
+#define TRACE_EMITLOADADDR_OFFSET 19
+#define TRACE_EMITLOADADDR_LENGTH 1
+#define TRACE_EMITLOADADDR (0x1 << TRACE_EMITLOADADDR_OFFSET)
+#define TRACE_EMITPRIV_OFFSET 18
+#define TRACE_EMITPRIV_LENGTH 1
+#define TRACE_EMITPRIV (0x1 << TRACE_EMITPRIV_OFFSET)
+#define TRACE_EMITBRANCH_OFFSET 17
+#define TRACE_EMITBRANCH_LENGTH 1
+#define TRACE_EMITBRANCH (0x1 << TRACE_EMITBRANCH_OFFSET)
+#define TRACE_EMITPC_OFFSET 16
+#define TRACE_EMITPC_LENGTH 1
+#define TRACE_EMITPC (0x1 << TRACE_EMITPC_OFFSET)
+#define TRACE_FULLACTION_OFFSET 8
+#define TRACE_FULLACTION_LENGTH 2
+#define TRACE_FULLACTION (0x3 << TRACE_FULLACTION_OFFSET)
+#define TRACE_DESTINATION_OFFSET 4
+#define TRACE_DESTINATION_LENGTH 2
+#define TRACE_DESTINATION (0x3 << TRACE_DESTINATION_OFFSET)
+#define TRACE_STALL_OFFSET 2
+#define TRACE_STALL_LENGTH 1
+#define TRACE_STALL (0x1 << TRACE_STALL_OFFSET)
+#define TRACE_DISCARD_OFFSET 1
+#define TRACE_DISCARD_LENGTH 1
+#define TRACE_DISCARD (0x1 << TRACE_DISCARD_OFFSET)
+#define TRACE_SUPPORTED_OFFSET 0
+#define TRACE_SUPPORTED_LENGTH 1
+#define TRACE_SUPPORTED (0x1 << TRACE_SUPPORTED_OFFSET)
+#define TBUFSTART 0x729
+#define TBUFEND 0x72a
+#define TBUFWRITE 0x72b
diff --git a/src/target/riscv/opcodes.h b/src/target/riscv/opcodes.h
index c3deab2..07eb853 100644
--- a/src/target/riscv/opcodes.h
+++ b/src/target/riscv/opcodes.h
@@ -5,6 +5,13 @@
#define S0 8
#define S1 9
+/*
+ * Disabling the warning we get when some opcodes functions aren't used. Not
+ * every user of this file uses every function, and it doesn't make sense to
+ * make them global. I suppose they could be macros.
+ */
+#pragma GCC diagnostic ignored "-Wunused-function"
+
static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
return (value >> lo) & ((1 << (hi+1-lo)) - 1);
}
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
new file mode 100644
index 0000000..e940d20
--- /dev/null
+++ b/src/target/riscv/riscv-011.c
@@ -0,0 +1,2601 @@
+/*
+ * Support for RISC-V, debug version 0.11. This was never an officially adopted
+ * spec, but SiFive made some silicon that uses it.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <time.h>
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "target.h"
+#include "target/algorithm.h"
+#include "target_type.h"
+#include "log.h"
+#include "jtag/jtag.h"
+#include "register.h"
+#include "breakpoints.h"
+#include "helper/time_support.h"
+#include "riscv.h"
+
+/**
+ * Since almost everything can be accomplish by scanning the dbus register, all
+ * functions here assume dbus is already selected. The exception are functions
+ * called directly by OpenOCD, which can't assume anything about what's
+ * currently in IR. They should set IR to dbus explicitly.
+ */
+
+/**
+ * Code structure
+ *
+ * At the bottom of the stack are the OpenOCD JTAG functions:
+ * jtag_add_[id]r_scan
+ * jtag_execute_query
+ * jtag_add_runtest
+ *
+ * There are a few functions to just instantly shift a register and get its
+ * value:
+ * dtmcontrol_scan
+ * idcode_scan
+ * dbus_scan
+ *
+ * Because doing one scan and waiting for the result is slow, most functions
+ * batch up a bunch of dbus writes and then execute them all at once. They use
+ * the scans "class" for this:
+ * scans_new
+ * scans_delete
+ * scans_execute
+ * scans_add_...
+ * Usually you new(), call a bunch of add functions, then execute() and look
+ * at the results by calling scans_get...()
+ *
+ * Optimized functions will directly use the scans class above, but slightly
+ * lazier code will use the cache functions that in turn use the scans
+ * functions:
+ * cache_get...
+ * cache_set...
+ * cache_write
+ * cache_set... update a local structure, which is then synced to the target
+ * with cache_write(). Only Debug RAM words that are actually changed are sent
+ * to the target. Afterwards use cache_get... to read results.
+ */
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+#define DIM(x) (sizeof(x)/sizeof(*x))
+
+// Constants for legacy SiFive hardware breakpoints.
+#define CSR_BPCONTROL_X (1<<0)
+#define CSR_BPCONTROL_W (1<<1)
+#define CSR_BPCONTROL_R (1<<2)
+#define CSR_BPCONTROL_U (1<<3)
+#define CSR_BPCONTROL_S (1<<4)
+#define CSR_BPCONTROL_H (1<<5)
+#define CSR_BPCONTROL_M (1<<6)
+#define CSR_BPCONTROL_BPMATCH (0xf<<7)
+#define CSR_BPCONTROL_BPACTION (0xff<<11)
+
+#define DEBUG_ROM_START 0x800
+#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
+#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
+#define DEBUG_RAM_START 0x400
+
+#define SETHALTNOT 0x10c
+
+/*** JTAG registers. ***/
+
+#define DTMCONTROL 0x10
+#define DTMCONTROL_DBUS_RESET (1<<16)
+#define DTMCONTROL_IDLE (7<<10)
+#define DTMCONTROL_ADDRBITS (0xf<<4)
+#define DTMCONTROL_VERSION (0xf)
+
+#define DBUS 0x11
+#define DBUS_OP_START 0
+#define DBUS_OP_SIZE 2
+typedef enum {
+ DBUS_OP_NOP = 0,
+ DBUS_OP_READ = 1,
+ DBUS_OP_WRITE = 2
+} dbus_op_t;
+typedef enum {
+ DBUS_STATUS_SUCCESS = 0,
+ DBUS_STATUS_FAILED = 2,
+ DBUS_STATUS_BUSY = 3
+} dbus_status_t;
+#define DBUS_DATA_START 2
+#define DBUS_DATA_SIZE 34
+#define DBUS_ADDRESS_START 36
+
+typedef enum {
+ RE_OK,
+ RE_FAIL,
+ RE_AGAIN
+} riscv_error_t;
+
+typedef enum slot {
+ SLOT0,
+ SLOT1,
+ SLOT_LAST,
+} slot_t;
+
+/*** Debug Bus registers. ***/
+
+#define DMCONTROL 0x10
+#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
+#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
+#define DMCONTROL_BUSERROR (7<<19)
+#define DMCONTROL_SERIAL (3<<16)
+#define DMCONTROL_AUTOINCREMENT (1<<15)
+#define DMCONTROL_ACCESS (7<<12)
+#define DMCONTROL_HARTID (0x3ff<<2)
+#define DMCONTROL_NDRESET (1<<1)
+#define DMCONTROL_FULLRESET 1
+
+#define DMINFO 0x11
+#define DMINFO_ABUSSIZE (0x7fU<<25)
+#define DMINFO_SERIALCOUNT (0xf<<21)
+#define DMINFO_ACCESS128 (1<<20)
+#define DMINFO_ACCESS64 (1<<19)
+#define DMINFO_ACCESS32 (1<<18)
+#define DMINFO_ACCESS16 (1<<17)
+#define DMINFO_ACCESS8 (1<<16)
+#define DMINFO_DRAMSIZE (0x3f<<10)
+#define DMINFO_AUTHENTICATED (1<<5)
+#define DMINFO_AUTHBUSY (1<<4)
+#define DMINFO_AUTHTYPE (3<<2)
+#define DMINFO_VERSION 3
+
+/*** Info about the core being debugged. ***/
+
+#define DBUS_ADDRESS_UNKNOWN 0xffff
+#define WALL_CLOCK_TIMEOUT 2
+
+// gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
+// its source tree. We must interpret the numbers the same here.
+enum {
+ REG_XPR0 = 0,
+ REG_XPR31 = 31,
+ REG_PC = 32,
+ REG_FPR0 = 33,
+ REG_FPR31 = 64,
+ REG_CSR0 = 65,
+ REG_MSTATUS = CSR_MSTATUS + REG_CSR0,
+ REG_CSR4095 = 4160,
+ REG_PRIV = 4161,
+ REG_COUNT
+};
+
+#define MAX_HWBPS 16
+#define DRAM_CACHE_SIZE 16
+
+struct trigger {
+ uint64_t address;
+ uint32_t length;
+ uint64_t mask;
+ uint64_t value;
+ bool read, write, execute;
+ int unique_id;
+};
+
+struct memory_cache_line {
+ uint32_t data;
+ bool valid;
+ bool dirty;
+};
+
+typedef struct {
+ /* Number of address bits in the dbus register. */
+ uint8_t addrbits;
+ /* Number of words in Debug RAM. */
+ unsigned int dramsize;
+ uint64_t dcsr;
+ uint64_t dpc;
+ uint64_t misa;
+ uint64_t tselect;
+ bool tselect_dirty;
+ /* The value that mstatus actually has on the target right now. This is not
+ * the value we present to the user. That one may be stored in the
+ * reg_cache. */
+ uint64_t mstatus_actual;
+
+ struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
+
+ /* Single buffer that contains all register names, instead of calling
+ * malloc for each register. Needs to be freed when reg_list is freed. */
+ char *reg_names;
+ /* Single buffer that contains all register values. */
+ void *reg_values;
+
+ // For each physical trigger, contains -1 if the hwbp is available, or the
+ // unique_id of the breakpoint/watchpoint that is using it.
+ int trigger_unique_id[MAX_HWBPS];
+
+ unsigned int trigger_count;
+
+ // Number of run-test/idle cycles the target requests we do after each dbus
+ // access.
+ unsigned int dtmcontrol_idle;
+
+ // This value is incremented every time a dbus access comes back as "busy".
+ // It's used to determine how many run-test/idle cycles to feed the target
+ // in between accesses.
+ unsigned int dbus_busy_delay;
+
+ // This value is incremented every time we read the debug interrupt as
+ // high. It's used to add extra run-test/idle cycles after setting debug
+ // interrupt high, so ideally we never have to perform a whole extra scan
+ // before the interrupt is cleared.
+ unsigned int interrupt_high_delay;
+
+ bool need_strict_step;
+ bool never_halted;
+} riscv011_info_t;
+
+typedef struct {
+ bool haltnot;
+ bool interrupt;
+} bits_t;
+
+/*** Necessary prototypes. ***/
+
+static int poll_target(struct target *target, bool announce);
+static int riscv011_poll(struct target *target);
+static int register_get(struct reg *reg);
+
+/*** Utility functions. ***/
+
+#define DEBUG_LENGTH 264
+
+static riscv011_info_t *get_info(const struct target *target)
+{
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ return (riscv011_info_t *) info->version_specific;
+}
+
+static unsigned int slot_offset(const struct target *target, slot_t slot)
+{
+ riscv011_info_t *info = get_info(target);
+ switch (xlen(target)) {
+ case 32:
+ switch (slot) {
+ case SLOT0: return 4;
+ case SLOT1: return 5;
+ case SLOT_LAST: return info->dramsize-1;
+ }
+ case 64:
+ switch (slot) {
+ case SLOT0: return 4;
+ case SLOT1: return 6;
+ case SLOT_LAST: return info->dramsize-2;
+ }
+ }
+ LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
+ xlen(target), slot);
+ assert(0);
+}
+
+static uint32_t load_slot(const struct target *target, unsigned int dest,
+ slot_t slot)
+{
+ unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ return load(target, dest, ZERO, offset);
+}
+
+static uint32_t store_slot(const struct target *target, unsigned int src,
+ slot_t slot)
+{
+ unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ return store(target, src, ZERO, offset);
+}
+
+static uint16_t dram_address(unsigned int index)
+{
+ if (index < 0x10)
+ return index;
+ else
+ return 0x40 + index - 0x10;
+}
+
+static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
+{
+ struct scan_field field;
+ uint8_t in_value[4];
+ uint8_t out_value[4];
+
+ buf_set_u32(out_value, 0, 32, out);
+
+ jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
+
+ field.num_bits = 32;
+ field.out_value = out_value;
+ field.in_value = in_value;
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ /* Always return to dbus. */
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ uint32_t in = buf_get_u32(field.in_value, 0, 32);
+ LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
+
+ return in;
+}
+
+static uint32_t idcode_scan(struct target *target)
+{
+ struct scan_field field;
+ uint8_t in_value[4];
+
+ jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
+
+ field.num_bits = 32;
+ field.out_value = NULL;
+ field.in_value = in_value;
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ /* Always return to dbus. */
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ uint32_t in = buf_get_u32(field.in_value, 0, 32);
+ LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
+
+ return in;
+}
+
+static void increase_dbus_busy_delay(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
+ LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
+ info->dtmcontrol_idle, info->dbus_busy_delay,
+ info->interrupt_high_delay);
+
+ dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
+}
+
+static void increase_interrupt_high_delay(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
+ LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
+ info->dtmcontrol_idle, info->dbus_busy_delay,
+ info->interrupt_high_delay);
+}
+
+static void add_dbus_scan(const struct target *target, struct scan_field *field,
+ uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
+ uint16_t address, uint64_t data)
+{
+ riscv011_info_t *info = get_info(target);
+
+ field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
+ field->in_value = in_value;
+ field->out_value = out_value;
+
+ buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
+ buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
+ buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
+
+ jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
+
+ int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
+ if (data & DMCONTROL_INTERRUPT) {
+ idle_count += info->interrupt_high_delay;
+ }
+
+ if (idle_count) {
+ jtag_add_runtest(idle_count, TAP_IDLE);
+ }
+}
+
+static void dump_field(const struct scan_field *field)
+{
+ static const char *op_string[] = {"nop", "r", "w", "?"};
+ static const char *status_string[] = {"+", "?", "F", "b"};
+
+ if (debug_level < LOG_LVL_DEBUG)
+ return;
+
+ uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
+ unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
+ char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
+ char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
+ unsigned int out_data = out >> 2;
+ unsigned int out_address = out >> DBUS_ADDRESS_START;
+ uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
+ unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
+ char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
+ char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
+ unsigned int in_data = in >> 2;
+ unsigned int in_address = in >> DBUS_ADDRESS_START;
+
+ log_printf_lf(LOG_LVL_DEBUG,
+ __FILE__, __LINE__, "scan",
+ "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
+ field->num_bits,
+ op_string[out_op], out_interrupt, out_haltnot, out_data,
+ out_address,
+ status_string[in_op], in_interrupt, in_haltnot, in_data,
+ in_address);
+}
+
+static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
+ uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
+{
+ riscv011_info_t *info = get_info(target);
+ uint8_t in[8] = {0};
+ uint8_t out[8];
+ struct scan_field field = {
+ .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
+ .out_value = out,
+ .in_value = in
+ };
+
+ assert(info->addrbits != 0);
+
+ buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
+ buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
+ buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
+
+ /* Assume dbus is already selected. */
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
+
+ if (idle_count) {
+ jtag_add_runtest(idle_count, TAP_IDLE);
+ }
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("dbus_scan failed jtag scan");
+ return retval;
+ }
+
+ if (data_in) {
+ *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
+ }
+
+ if (address_in) {
+ *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
+ }
+
+ dump_field(&field);
+
+ return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
+}
+
+static uint64_t dbus_read(struct target *target, uint16_t address)
+{
+ uint64_t value;
+ dbus_status_t status;
+ uint16_t address_in;
+
+ unsigned i = 0;
+ do {
+ status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
+ if (status == DBUS_STATUS_BUSY) {
+ increase_dbus_busy_delay(target);
+ }
+ } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
+ i++ < 256);
+
+ if (status != DBUS_STATUS_SUCCESS) {
+ LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
+ }
+
+ return value;
+}
+
+static void dbus_write(struct target *target, uint16_t address, uint64_t value)
+{
+ dbus_status_t status = DBUS_STATUS_BUSY;
+ unsigned i = 0;
+ while (status == DBUS_STATUS_BUSY && i++ < 256) {
+ status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
+ if (status == DBUS_STATUS_BUSY) {
+ increase_dbus_busy_delay(target);
+ }
+ }
+ if (status != DBUS_STATUS_SUCCESS) {
+ LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
+ }
+}
+
+/*** scans "class" ***/
+
+typedef struct {
+ // Number of scans that space is reserved for.
+ unsigned int scan_count;
+ // Size reserved in memory for each scan, in bytes.
+ unsigned int scan_size;
+ unsigned int next_scan;
+ uint8_t *in;
+ uint8_t *out;
+ struct scan_field *field;
+ const struct target *target;
+} scans_t;
+
+static scans_t *scans_new(struct target *target, unsigned int scan_count)
+{
+ scans_t *scans = malloc(sizeof(scans_t));
+ scans->scan_count = scan_count;
+ // This code also gets called before xlen is detected.
+ if (xlen(target))
+ scans->scan_size = 2 + xlen(target) / 8;
+ else
+ scans->scan_size = 2 + 128 / 8;
+ scans->next_scan = 0;
+ scans->in = calloc(scans->scan_size, scans->scan_count);
+ scans->out = calloc(scans->scan_size, scans->scan_count);
+ scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
+ scans->target = target;
+ return scans;
+}
+
+static scans_t *scans_delete(scans_t *scans)
+{
+ assert(scans);
+ free(scans->field);
+ free(scans->out);
+ free(scans->in);
+ free(scans);
+ return NULL;
+}
+
+static void scans_reset(scans_t *scans)
+{
+ scans->next_scan = 0;
+}
+
+static void scans_dump(scans_t *scans)
+{
+ for (unsigned int i = 0; i < scans->next_scan; i++) {
+ dump_field(&scans->field[i]);
+ }
+}
+
+static int scans_execute(scans_t *scans)
+{
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ scans_dump(scans);
+
+ return ERROR_OK;
+}
+
+/** Add a 32-bit dbus write to the scans structure. */
+static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
+ bool set_interrupt)
+{
+ const unsigned int i = scans->next_scan;
+ int data_offset = scans->scan_size * i;
+ add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
+ scans->in + data_offset, DBUS_OP_WRITE, address,
+ (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
+ scans->next_scan++;
+ assert(scans->next_scan <= scans->scan_count);
+}
+
+/** Add a 32-bit dbus write for an instruction that jumps to the beginning of
+ * debug RAM. */
+static void scans_add_write_jump(scans_t *scans, uint16_t address,
+ bool set_interrupt)
+{
+ scans_add_write32(scans, address,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus write for an instruction that loads from the indicated
+ * slot. */
+static void scans_add_write_load(scans_t *scans, uint16_t address,
+ unsigned int reg, slot_t slot, bool set_interrupt)
+{
+ scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus write for an instruction that stores to the indicated
+ * slot. */
+static void scans_add_write_store(scans_t *scans, uint16_t address,
+ unsigned int reg, slot_t slot, bool set_interrupt)
+{
+ scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus read. */
+static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
+{
+ assert(scans->next_scan < scans->scan_count);
+ const unsigned int i = scans->next_scan;
+ int data_offset = scans->scan_size * i;
+ add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
+ scans->in + data_offset, DBUS_OP_READ, address,
+ (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
+ scans->next_scan++;
+}
+
+/** Add one or more scans to read the indicated slot. */
+static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
+{
+ const struct target *target = scans->target;
+ switch (xlen(target)) {
+ case 32:
+ scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
+ break;
+ case 64:
+ scans_add_read32(scans, slot_offset(target, slot), false);
+ scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
+ break;
+ }
+}
+
+static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
+ unsigned first, unsigned num)
+{
+ return buf_get_u32(scans->in + scans->scan_size * index, first, num);
+}
+
+static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
+ unsigned first, unsigned num)
+{
+ return buf_get_u64(scans->in + scans->scan_size * index, first, num);
+}
+
+/*** end of scans class ***/
+
+static uint32_t dram_read32(struct target *target, unsigned int index)
+{
+ uint16_t address = dram_address(index);
+ uint32_t value = dbus_read(target, address);
+ return value;
+}
+
+static void dram_write32(struct target *target, unsigned int index, uint32_t value,
+ bool set_interrupt)
+{
+ uint64_t dbus_value = DMCONTROL_HALTNOT | value;
+ if (set_interrupt)
+ dbus_value |= DMCONTROL_INTERRUPT;
+ dbus_write(target, dram_address(index), dbus_value);
+}
+
+/** Read the haltnot and interrupt bits. */
+static bits_t read_bits(struct target *target)
+{
+ uint64_t value;
+ dbus_status_t status;
+ uint16_t address_in;
+ riscv011_info_t *info = get_info(target);
+
+ bits_t err_result = {
+ .haltnot = 0,
+ .interrupt = 0
+ };
+
+ do {
+ unsigned i = 0;
+ do {
+ status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
+ if (status == DBUS_STATUS_BUSY) {
+ if (address_in == (1<<info->addrbits) - 1 &&
+ value == (1ULL<<DBUS_DATA_SIZE) - 1) {
+ LOG_ERROR("TDO seems to be stuck high.");
+ return err_result;
+ }
+ increase_dbus_busy_delay(target);
+ }
+ } while (status == DBUS_STATUS_BUSY && i++ < 256);
+
+ if (i >= 256) {
+ LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
+ return err_result;
+ }
+ } while (address_in > 0x10 && address_in != DMCONTROL);
+
+ bits_t result = {
+ .haltnot = get_field(value, DMCONTROL_HALTNOT),
+ .interrupt = get_field(value, DMCONTROL_INTERRUPT)
+ };
+ return result;
+}
+
+static int wait_for_debugint_clear(struct target *target, bool ignore_first)
+{
+ time_t start = time(NULL);
+ if (ignore_first) {
+ // Throw away the results of the first read, since they'll contain the
+ // result of the read that happened just before debugint was set.
+ // (Assuming the last scan before calling this function was one that
+ // sets debugint.)
+ read_bits(target);
+ }
+ while (1) {
+ bits_t bits = read_bits(target);
+ if (!bits.interrupt) {
+ return ERROR_OK;
+ }
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for debug int to clear.");
+ return ERROR_FAIL;
+ }
+ }
+}
+
+static int dram_check32(struct target *target, unsigned int index,
+ uint32_t expected)
+{
+ uint16_t address = dram_address(index);
+ uint32_t actual = dbus_read(target, address);
+ if (expected != actual) {
+ LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
+ expected, index, actual);
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static void cache_set32(struct target *target, unsigned int index, uint32_t data)
+{
+ riscv011_info_t *info = get_info(target);
+ if (info->dram_cache[index].valid &&
+ info->dram_cache[index].data == data) {
+ // This is already preset on the target.
+ LOG_DEBUG("cache[0x%x] = 0x%x (hit)", index, data);
+ return;
+ }
+ LOG_DEBUG("cache[0x%x] = 0x%x", index, data);
+ info->dram_cache[index].data = data;
+ info->dram_cache[index].valid = true;
+ info->dram_cache[index].dirty = true;
+}
+
+static void cache_set(struct target *target, slot_t slot, uint64_t data)
+{
+ unsigned int offset = slot_offset(target, slot);
+ cache_set32(target, offset, data);
+ if (xlen(target) > 32) {
+ cache_set32(target, offset + 1, data >> 32);
+ }
+}
+
+static void cache_set_jump(struct target *target, unsigned int index)
+{
+ cache_set32(target, index,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
+}
+
+static void cache_set_load(struct target *target, unsigned int index,
+ unsigned int reg, slot_t slot)
+{
+ uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ cache_set32(target, index, load(target, reg, ZERO, offset));
+}
+
+static void cache_set_store(struct target *target, unsigned int index,
+ unsigned int reg, slot_t slot)
+{
+ uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ cache_set32(target, index, store(target, reg, ZERO, offset));
+}
+
+static void dump_debug_ram(struct target *target)
+{
+ for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
+ uint32_t value = dram_read32(target, i);
+ LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
+ }
+}
+
+/* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
+static void cache_invalidate(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ info->dram_cache[i].valid = false;
+ info->dram_cache[i].dirty = false;
+ }
+}
+
+/* Called by cache_write() after the program has run. Also call this if you're
+ * running programs without calling cache_write(). */
+static void cache_clean(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (i >= 4) {
+ info->dram_cache[i].valid = false;
+ }
+ info->dram_cache[i].dirty = false;
+ }
+}
+
+static int cache_check(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ int error = 0;
+
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
+ if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK) {
+ error++;
+ }
+ }
+ }
+
+ if (error) {
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+/** Write cache to the target, and optionally run the program.
+ * Then read the value at address into the cache, assuming address < 128. */
+#define CACHE_NO_READ 128
+static int cache_write(struct target *target, unsigned int address, bool run)
+{
+ LOG_DEBUG("enter");
+ riscv011_info_t *info = get_info(target);
+ scans_t *scans = scans_new(target, info->dramsize + 2);
+
+ unsigned int last = info->dramsize;
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].dirty) {
+ last = i;
+ }
+ }
+
+ if (last == info->dramsize) {
+ // Nothing needs to be written to RAM.
+ dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT);
+
+ } else {
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].dirty) {
+ bool set_interrupt = (i == last && run);
+ scans_add_write32(scans, i, info->dram_cache[i].data,
+ set_interrupt);
+ }
+ }
+ }
+
+ if (run || address < CACHE_NO_READ) {
+ // Throw away the results of the first read, since it'll contain the
+ // result of the read that happened just before debugint was set.
+ scans_add_read32(scans, address, false);
+
+ // This scan contains the results of the read the caller requested, as
+ // well as an interrupt bit worth looking at.
+ scans_add_read32(scans, address, false);
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed.");
+ return retval;
+ }
+
+ int errors = 0;
+ for (unsigned int i = 0; i < scans->next_scan; i++) {
+ dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ return ERROR_FAIL;
+ case DBUS_STATUS_BUSY:
+ errors++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ }
+
+ if (errors) {
+ increase_dbus_busy_delay(target);
+
+ // Try again, using the slow careful code.
+ // Write all RAM, just to be extra cautious.
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (i == last && run) {
+ dram_write32(target, last, info->dram_cache[last].data, true);
+ } else {
+ dram_write32(target, i, info->dram_cache[i].data, false);
+ }
+ info->dram_cache[i].dirty = false;
+ }
+ if (run) {
+ cache_clean(target);
+ }
+
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+
+ } else {
+ if (run) {
+ cache_clean(target);
+ } else {
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ info->dram_cache[i].dirty = false;
+ }
+ }
+
+ if (run || address < CACHE_NO_READ) {
+ int interrupt = scans_get_u32(scans, scans->next_scan-1,
+ DBUS_DATA_START + 33, 1);
+ if (interrupt) {
+ increase_interrupt_high_delay(target);
+ // Slow path wait for it to clear.
+ if (wait_for_debugint_clear(target, false) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+ } else {
+ // We read a useful value in that last scan.
+ unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
+ DBUS_ADDRESS_START, info->addrbits);
+ if (read_addr != address) {
+ LOG_INFO("Got data from 0x%x but expected it from 0x%x",
+ read_addr, address);
+ }
+ info->dram_cache[read_addr].data =
+ scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
+ info->dram_cache[read_addr].valid = true;
+ }
+ }
+ }
+
+ scans_delete(scans);
+ LOG_DEBUG("exit");
+
+ return ERROR_OK;
+}
+
+static uint32_t cache_get32(struct target *target, unsigned int address)
+{
+ riscv011_info_t *info = get_info(target);
+ if (!info->dram_cache[address].valid) {
+ info->dram_cache[address].data = dram_read32(target, address);
+ info->dram_cache[address].valid = true;
+ }
+ return info->dram_cache[address].data;
+}
+
+static uint64_t cache_get(struct target *target, slot_t slot)
+{
+ unsigned int offset = slot_offset(target, slot);
+ uint64_t value = cache_get32(target, offset);
+ if (xlen(target) > 32) {
+ value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
+ }
+ return value;
+}
+
+/* Write instruction that jumps from the specified word in Debug RAM to resume
+ * in Debug ROM. */
+static void dram_write_jump(struct target *target, unsigned int index,
+ bool set_interrupt)
+{
+ dram_write32(target, index,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
+ set_interrupt);
+}
+
+static int wait_for_state(struct target *target, enum target_state state)
+{
+ time_t start = time(NULL);
+ while (1) {
+ int result = riscv011_poll(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ if (target->state == state) {
+ return ERROR_OK;
+ }
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for state %d.", state);
+ return ERROR_FAIL;
+ }
+ }
+}
+
+static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
+{
+ cache_set32(target, 0, csrr(S0, csr));
+ cache_set_store(target, 1, S0, SLOT0);
+ cache_set_jump(target, 2);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ *value = cache_get(target, SLOT0);
+ LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
+
+ return ERROR_OK;
+}
+
+static int write_csr(struct target *target, uint32_t csr, uint64_t value)
+{
+ LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, csr));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
+{
+ cache_set_load(target, 0, gpr, SLOT0);
+ cache_set_jump(target, 1);
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static int maybe_read_tselect(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+
+ if (info->tselect_dirty) {
+ int result = read_csr(target, &info->tselect, CSR_TSELECT);
+ if (result != ERROR_OK)
+ return result;
+ info->tselect_dirty = false;
+ }
+
+ return ERROR_OK;
+}
+
+static int maybe_write_tselect(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+
+ if (!info->tselect_dirty) {
+ int result = write_csr(target, CSR_TSELECT, info->tselect);
+ if (result != ERROR_OK)
+ return result;
+ info->tselect_dirty = true;
+ }
+
+ return ERROR_OK;
+}
+
+static int execute_resume(struct target *target, bool step)
+{
+ riscv011_info_t *info = get_info(target);
+
+ LOG_DEBUG("step=%d", step);
+
+ maybe_write_tselect(target);
+
+ // TODO: check if dpc is dirty (which also is true if an exception was hit
+ // at any time)
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_DPC));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, info->dpc);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
+ if (mstatus_reg->valid) {
+ uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, xlen(target));
+ if (mstatus_user != info->mstatus_actual) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, mstatus_user);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ }
+ }
+
+ info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
+ info->dcsr &= ~DCSR_HALT;
+
+ if (step) {
+ info->dcsr |= DCSR_STEP;
+ } else {
+ info->dcsr &= ~DCSR_STEP;
+ }
+
+ dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
+ dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
+ dram_write32(target, 2, fence_i(), false);
+ dram_write_jump(target, 3, false);
+
+ // Write DCSR value, set interrupt and clear haltnot.
+ uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
+ dbus_write(target, dram_address(4), dbus_value);
+
+ cache_invalidate(target);
+
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ return ERROR_FAIL;
+ }
+
+ target->state = TARGET_RUNNING;
+ register_cache_invalidate(target->reg_cache);
+
+ return ERROR_OK;
+}
+
+// Execute a step, and wait for reentry into Debug Mode.
+static int full_step(struct target *target, bool announce)
+{
+ int result = execute_resume(target, true);
+ if (result != ERROR_OK)
+ return result;
+ time_t start = time(NULL);
+ while (1) {
+ result = poll_target(target, announce);
+ if (result != ERROR_OK)
+ return result;
+ if (target->state != TARGET_DEBUG_RUNNING)
+ break;
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for step to complete.");
+ return ERROR_FAIL;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int resume(struct target *target, int debug_execution, bool step)
+{
+ if (debug_execution) {
+ LOG_ERROR("TODO: debug_execution is true");
+ return ERROR_FAIL;
+ }
+
+ return execute_resume(target, step);
+}
+
+/** Update register sizes based on xlen. */
+static void update_reg_list(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ if (info->reg_values) {
+ free(info->reg_values);
+ }
+ info->reg_values = malloc(REG_COUNT * xlen(target) / 4);
+
+ for (unsigned int i = 0; i < REG_COUNT; i++) {
+ struct reg *r = &target->reg_cache->reg_list[i];
+ r->value = info->reg_values + i * xlen(target) / 4;
+ if (r->dirty) {
+ LOG_ERROR("Register %d was dirty. Its value is lost.", i);
+ }
+ if (i == REG_PRIV) {
+ r->size = 8;
+ } else {
+ r->size = xlen(target);
+ }
+ r->valid = false;
+ }
+}
+
+static uint64_t reg_cache_get(struct target *target, unsigned int number)
+{
+ struct reg *r = &target->reg_cache->reg_list[number];
+ if (!r->valid) {
+ LOG_ERROR("Register cache entry for %d is invalid!", number);
+ assert(r->valid);
+ }
+ uint64_t value = buf_get_u64(r->value, 0, r->size);
+ LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
+ return value;
+}
+
+static void reg_cache_set(struct target *target, unsigned int number,
+ uint64_t value)
+{
+ struct reg *r = &target->reg_cache->reg_list[number];
+ LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
+ r->valid = true;
+ buf_set_u64(r->value, 0, r->size, value);
+}
+
+static int update_mstatus_actual(struct target *target)
+{
+ struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
+ if (mstatus_reg->valid) {
+ // We previously made it valid.
+ return ERROR_OK;
+ }
+
+ // Force reading the register. In that process mstatus_actual will be
+ // updated.
+ return register_get(&target->reg_cache->reg_list[REG_MSTATUS]);
+}
+
+/*** OpenOCD target functions. ***/
+
+static int register_get(struct reg *reg)
+{
+ struct target *target = (struct target *) reg->arch_info;
+ riscv011_info_t *info = get_info(target);
+
+ maybe_write_tselect(target);
+
+ if (reg->number <= REG_XPR31) {
+ buf_set_u64(reg->value, 0, xlen(target), reg_cache_get(target, reg->number));
+ LOG_DEBUG("%s=0x%" PRIx64, reg->name, reg_cache_get(target, reg->number));
+ return ERROR_OK;
+ } else if (reg->number == REG_PC) {
+ buf_set_u32(reg->value, 0, 32, info->dpc);
+ reg->valid = true;
+ LOG_DEBUG("%s=0x%" PRIx64 " (cached)", reg->name, info->dpc);
+ return ERROR_OK;
+ } else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
+ int result = update_mstatus_actual(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ unsigned i = 0;
+ if ((info->mstatus_actual & MSTATUS_FS) == 0) {
+ info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
+ cache_set_load(target, i++, S0, SLOT1);
+ cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
+ cache_set(target, SLOT1, info->mstatus_actual);
+ }
+
+ if (xlen(target) == 32) {
+ cache_set32(target, i++, fsw(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ } else {
+ cache_set32(target, i++, fsd(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ }
+ cache_set_jump(target, i++);
+ } else if (reg->number >= REG_CSR0 && reg->number <= REG_CSR4095) {
+ cache_set32(target, 0, csrr(S0, reg->number - REG_CSR0));
+ cache_set_store(target, 1, S0, SLOT0);
+ cache_set_jump(target, 2);
+ } else if (reg->number == REG_PRIV) {
+ buf_set_u64(reg->value, 0, 8, get_field(info->dcsr, DCSR_PRV));
+ LOG_DEBUG("%s=%d (cached)", reg->name,
+ (int) get_field(info->dcsr, DCSR_PRV));
+ return ERROR_OK;
+ } else {
+ LOG_ERROR("Don't know how to read register %d (%s)", reg->number, reg->name);
+ return ERROR_FAIL;
+ }
+
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ if (exception) {
+ LOG_ERROR("Got exception 0x%x when reading register %d", exception,
+ reg->number);
+ buf_set_u64(reg->value, 0, xlen(target), ~0);
+ return ERROR_FAIL;
+ }
+
+ uint64_t value = cache_get(target, SLOT0);
+ LOG_DEBUG("%s=0x%" PRIx64, reg->name, value);
+ buf_set_u64(reg->value, 0, xlen(target), value);
+
+ if (reg->number == REG_MSTATUS) {
+ info->mstatus_actual = value;
+ reg->valid = true;
+ }
+
+ return ERROR_OK;
+}
+
+static int register_write(struct target *target, unsigned int number,
+ uint64_t value)
+{
+ riscv011_info_t *info = get_info(target);
+
+ maybe_write_tselect(target);
+
+ if (number == S0) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
+ cache_set_jump(target, 2);
+ } else if (number == S1) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set_store(target, 1, S0, SLOT_LAST);
+ cache_set_jump(target, 2);
+ } else if (number <= REG_XPR31) {
+ cache_set_load(target, 0, number - REG_XPR0, SLOT0);
+ cache_set_jump(target, 1);
+ } else if (number == REG_PC) {
+ info->dpc = value;
+ return ERROR_OK;
+ } else if (number >= REG_FPR0 && number <= REG_FPR31) {
+ int result = update_mstatus_actual(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ unsigned i = 0;
+ if ((info->mstatus_actual & MSTATUS_FS) == 0) {
+ info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
+ cache_set_load(target, i++, S0, SLOT1);
+ cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
+ cache_set(target, SLOT1, info->mstatus_actual);
+ }
+
+ if (xlen(target) == 32) {
+ cache_set32(target, i++, flw(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ } else {
+ cache_set32(target, i++, fld(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ }
+ cache_set_jump(target, i++);
+ } else if (number >= REG_CSR0 && number <= REG_CSR4095) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, number - REG_CSR0));
+ cache_set_jump(target, 2);
+
+ if (number == REG_MSTATUS) {
+ info->mstatus_actual = value;
+ }
+ } else if (number == REG_PRIV) {
+ info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
+ return ERROR_OK;
+ } else {
+ LOG_ERROR("Don't know how to write register %d", number);
+ return ERROR_FAIL;
+ }
+
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, info->dramsize - 1, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ if (exception) {
+ LOG_ERROR("Got exception 0x%x when writing register %d", exception,
+ number);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int register_set(struct reg *reg, uint8_t *buf)
+{
+ struct target *target = (struct target *) reg->arch_info;
+
+ uint64_t value = buf_get_u64(buf, 0, xlen(target));
+
+ LOG_DEBUG("write 0x%" PRIx64 " to %s", value, reg->name);
+ struct reg *r = &target->reg_cache->reg_list[reg->number];
+ r->valid = true;
+ memcpy(r->value, buf, (r->size + 7) / 8);
+
+ return register_write(target, reg->number, value);
+}
+
+static struct reg_arch_type riscv_reg_arch_type = {
+ .get = register_get,
+ .set = register_set
+};
+
+static int halt(struct target *target)
+{
+ LOG_DEBUG("riscv_halt()");
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
+ cache_set32(target, 1, csrr(S0, CSR_MHARTID));
+ cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
+ cache_set_jump(target, 3);
+
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ LOG_ERROR("cache_write() failed.");
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int init_target(struct command_context *cmd_ctx,
+ struct target *target)
+{
+ LOG_DEBUG("init");
+ riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
+ generic_info->version_specific = calloc(1, sizeof(riscv011_info_t));
+ if (!generic_info->version_specific)
+ return ERROR_FAIL;
+ riscv011_info_t *info = get_info(target);
+
+ target->reg_cache = calloc(1, sizeof(*target->reg_cache));
+ target->reg_cache->name = "RISC-V registers";
+ target->reg_cache->num_regs = REG_COUNT;
+
+ target->reg_cache->reg_list = calloc(REG_COUNT, sizeof(struct reg));
+
+ const unsigned int max_reg_name_len = 12;
+ info->reg_names = calloc(1, REG_COUNT * max_reg_name_len);
+ char *reg_name = info->reg_names;
+ info->reg_values = NULL;
+
+ for (unsigned int i = 0; i < REG_COUNT; i++) {
+ struct reg *r = &target->reg_cache->reg_list[i];
+ r->number = i;
+ r->caller_save = true;
+ r->dirty = false;
+ r->valid = false;
+ r->exist = true;
+ r->type = &riscv_reg_arch_type;
+ r->arch_info = target;
+ if (i <= REG_XPR31) {
+ sprintf(reg_name, "x%d", i);
+ } else if (i == REG_PC) {
+ sprintf(reg_name, "pc");
+ } else if (i >= REG_FPR0 && i <= REG_FPR31) {
+ sprintf(reg_name, "f%d", i - REG_FPR0);
+ } else if (i >= REG_CSR0 && i <= REG_CSR4095) {
+ sprintf(reg_name, "csr%d", i - REG_CSR0);
+ } else if (i == REG_PRIV) {
+ sprintf(reg_name, "priv");
+ }
+ if (reg_name[0]) {
+ r->name = reg_name;
+ }
+ reg_name += strlen(reg_name) + 1;
+ assert(reg_name < info->reg_names + REG_COUNT * max_reg_name_len);
+ }
+ update_reg_list(target);
+
+ memset(info->trigger_unique_id, 0xff, sizeof(info->trigger_unique_id));
+
+ return ERROR_OK;
+}
+
+static void deinit_target(struct target *target)
+{
+ LOG_DEBUG("riscv_deinit_target()");
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ free(info->version_specific);
+ info->version_specific = NULL;
+}
+
+static int add_trigger(struct target *target, struct trigger *trigger)
+{
+ riscv011_info_t *info = get_info(target);
+
+ maybe_read_tselect(target);
+
+ unsigned int i;
+ for (i = 0; i < info->trigger_count; i++) {
+ if (info->trigger_unique_id[i] != -1) {
+ continue;
+ }
+
+ write_csr(target, CSR_TSELECT, i);
+
+ uint64_t tdata1;
+ read_csr(target, &tdata1, CSR_TDATA1);
+ int type = get_field(tdata1, MCONTROL_TYPE(xlen(target)));
+
+ if (type != 2) {
+ continue;
+ }
+
+ if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
+ // Trigger is already in use, presumably by user code.
+ continue;
+ }
+
+ // address/data match trigger
+ tdata1 |= MCONTROL_DMODE(xlen(target));
+ tdata1 = set_field(tdata1, MCONTROL_ACTION,
+ MCONTROL_ACTION_DEBUG_MODE);
+ tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
+ tdata1 |= MCONTROL_M;
+ if (info->misa & (1 << ('H' - 'A')))
+ tdata1 |= MCONTROL_H;
+ if (info->misa & (1 << ('S' - 'A')))
+ tdata1 |= MCONTROL_S;
+ if (info->misa & (1 << ('U' - 'A')))
+ tdata1 |= MCONTROL_U;
+
+ if (trigger->execute)
+ tdata1 |= MCONTROL_EXECUTE;
+ if (trigger->read)
+ tdata1 |= MCONTROL_LOAD;
+ if (trigger->write)
+ tdata1 |= MCONTROL_STORE;
+
+ write_csr(target, CSR_TDATA1, tdata1);
+
+ uint64_t tdata1_rb;
+ read_csr(target, &tdata1_rb, CSR_TDATA1);
+ LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
+
+ if (tdata1 != tdata1_rb) {
+ LOG_DEBUG("Trigger %d doesn't support what we need; After writing 0x%"
+ PRIx64 " to tdata1 it contains 0x%" PRIx64,
+ i, tdata1, tdata1_rb);
+ write_csr(target, CSR_TDATA1, 0);
+ continue;
+ }
+
+ write_csr(target, CSR_TDATA2, trigger->address);
+
+ LOG_DEBUG("Using resource %d for bp %d", i,
+ trigger->unique_id);
+ info->trigger_unique_id[i] = trigger->unique_id;
+ break;
+ }
+ if (i >= info->trigger_count) {
+ LOG_ERROR("Couldn't find an available hardware trigger.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ return ERROR_OK;
+}
+
+static int remove_trigger(struct target *target, struct trigger *trigger)
+{
+ riscv011_info_t *info = get_info(target);
+
+ maybe_read_tselect(target);
+
+ unsigned int i;
+ for (i = 0; i < info->trigger_count; i++) {
+ if (info->trigger_unique_id[i] == trigger->unique_id) {
+ break;
+ }
+ }
+ if (i >= info->trigger_count) {
+ LOG_ERROR("Couldn't find the hardware resources used by hardware "
+ "trigger.");
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
+ write_csr(target, CSR_TSELECT, i);
+ write_csr(target, CSR_TDATA1, 0);
+ info->trigger_unique_id[i] = -1;
+
+ return ERROR_OK;
+}
+
+static void trigger_from_breakpoint(struct trigger *trigger,
+ const struct breakpoint *breakpoint)
+{
+ trigger->address = breakpoint->address;
+ trigger->length = breakpoint->length;
+ trigger->mask = ~0LL;
+ trigger->read = false;
+ trigger->write = false;
+ trigger->execute = true;
+ // unique_id is unique across both breakpoints and watchpoints.
+ trigger->unique_id = breakpoint->unique_id;
+}
+
+static void trigger_from_watchpoint(struct trigger *trigger,
+ const struct watchpoint *watchpoint)
+{
+ trigger->address = watchpoint->address;
+ trigger->length = watchpoint->length;
+ trigger->mask = watchpoint->mask;
+ trigger->value = watchpoint->value;
+ trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
+ trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
+ trigger->execute = false;
+ // unique_id is unique across both breakpoints and watchpoints.
+ trigger->unique_id = watchpoint->unique_id;
+}
+
+static int add_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ if (breakpoint->type == BKPT_SOFT) {
+ if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
+ breakpoint->orig_instr) != ERROR_OK) {
+ LOG_ERROR("Failed to read original instruction at 0x%x",
+ breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ int retval;
+ if (breakpoint->length == 4) {
+ retval = target_write_u32(target, breakpoint->address, ebreak());
+ } else {
+ retval = target_write_u16(target, breakpoint->address, ebreak_c());
+ }
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%x",
+ breakpoint->length, breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ } else if (breakpoint->type == BKPT_HARD) {
+ struct trigger trigger;
+ trigger_from_breakpoint(&trigger, breakpoint);
+ int result = add_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ } else {
+ LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ breakpoint->set = true;
+
+ return ERROR_OK;
+}
+
+static int remove_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ if (breakpoint->type == BKPT_SOFT) {
+ if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
+ breakpoint->orig_instr) != ERROR_OK) {
+ LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
+ "0x%x", breakpoint->length, breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ } else if (breakpoint->type == BKPT_HARD) {
+ struct trigger trigger;
+ trigger_from_breakpoint(&trigger, breakpoint);
+ int result = remove_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ } else {
+ LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ breakpoint->set = false;
+
+ return ERROR_OK;
+}
+
+static int add_watchpoint(struct target *target,
+ struct watchpoint *watchpoint)
+{
+ struct trigger trigger;
+ trigger_from_watchpoint(&trigger, watchpoint);
+
+ int result = add_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ watchpoint->set = true;
+
+ return ERROR_OK;
+}
+
+static int remove_watchpoint(struct target *target,
+ struct watchpoint *watchpoint)
+{
+ struct trigger trigger;
+ trigger_from_watchpoint(&trigger, watchpoint);
+
+ int result = remove_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ watchpoint->set = false;
+
+ return ERROR_OK;
+}
+
+static int strict_step(struct target *target, bool announce)
+{
+ riscv011_info_t *info = get_info(target);
+
+ LOG_DEBUG("enter");
+
+ struct breakpoint *breakpoint = target->breakpoints;
+ while (breakpoint) {
+ remove_breakpoint(target, breakpoint);
+ breakpoint = breakpoint->next;
+ }
+
+ struct watchpoint *watchpoint = target->watchpoints;
+ while (watchpoint) {
+ remove_watchpoint(target, watchpoint);
+ watchpoint = watchpoint->next;
+ }
+
+ int result = full_step(target, announce);
+ if (result != ERROR_OK)
+ return result;
+
+ breakpoint = target->breakpoints;
+ while (breakpoint) {
+ add_breakpoint(target, breakpoint);
+ breakpoint = breakpoint->next;
+ }
+
+ watchpoint = target->watchpoints;
+ while (watchpoint) {
+ add_watchpoint(target, watchpoint);
+ watchpoint = watchpoint->next;
+ }
+
+ info->need_strict_step = false;
+
+ return ERROR_OK;
+}
+
+static int step(struct target *target, int current, uint32_t address,
+ int handle_breakpoints)
+{
+ riscv011_info_t *info = get_info(target);
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ if (!current) {
+ if (xlen(target) > 32) {
+ LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
+ xlen(target));
+ }
+ int result = register_write(target, REG_PC, address);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ if (info->need_strict_step || handle_breakpoints) {
+ int result = strict_step(target, true);
+ if (result != ERROR_OK)
+ return result;
+ } else {
+ return resume(target, 0, true);
+ }
+
+ return ERROR_OK;
+}
+
+static int examine(struct target *target)
+{
+ // Don't need to select dbus, since the first thing we do is read dtmcontrol.
+
+ uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
+ LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
+ LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
+ LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
+ LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
+ if (dtmcontrol == 0) {
+ LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
+ return ERROR_FAIL;
+ }
+ if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
+ LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
+ get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
+ return ERROR_FAIL;
+ }
+
+ riscv011_info_t *info = get_info(target);
+ info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
+ info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
+ if (info->dtmcontrol_idle == 0) {
+ // Some old SiFive cores don't set idle but need it to be 1.
+ uint32_t idcode = idcode_scan(target);
+ if (idcode == 0x10e31913)
+ info->dtmcontrol_idle = 1;
+ }
+
+ uint32_t dminfo = dbus_read(target, DMINFO);
+ LOG_DEBUG("dminfo: 0x%08x", dminfo);
+ LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
+ LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
+ LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
+ LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
+ LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
+ LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
+ LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
+ LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
+ LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
+ LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
+ LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
+ LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
+
+ if (get_field(dminfo, DMINFO_VERSION) != 1) {
+ LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
+ "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
+ return ERROR_FAIL;
+ }
+
+ info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
+
+ if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
+ LOG_ERROR("Authentication required by RISC-V core but not "
+ "supported by OpenOCD. dminfo=0x%x", dminfo);
+ return ERROR_FAIL;
+ }
+
+ // Figure out XLEN, and test writing all of Debug RAM while we're at it.
+ cache_set32(target, 0, xori(S1, ZERO, -1));
+ // 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
+ cache_set32(target, 1, srli(S1, S1, 31));
+ // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
+ cache_set32(target, 3, srli(S1, S1, 31));
+ // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
+ cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
+ cache_set_jump(target, 5);
+ for (unsigned i = 6; i < info->dramsize; i++) {
+ cache_set32(target, i, i * 0x01020304);
+ }
+
+ cache_write(target, 0, false);
+
+ // Check that we can actually read/write dram.
+ if (cache_check(target) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ cache_write(target, 0, true);
+ cache_invalidate(target);
+
+ uint32_t word0 = cache_get32(target, 0);
+ uint32_t word1 = cache_get32(target, 1);
+ riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
+ if (word0 == 1 && word1 == 0) {
+ generic_info->xlen = 32;
+ } else if (word0 == 0xffffffff && word1 == 3) {
+ generic_info->xlen = 64;
+ } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
+ generic_info->xlen = 128;
+ } else {
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
+ word0, word1, exception);
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("Discovered XLEN is %d", xlen(target));
+
+ // Update register list to match discovered XLEN.
+ update_reg_list(target);
+
+ if (read_csr(target, &info->misa, CSR_MISA) != ERROR_OK) {
+ LOG_ERROR("Failed to read misa.");
+ return ERROR_FAIL;
+ }
+
+ info->never_halted = true;
+
+ int result = riscv011_poll(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ target_set_examined(target);
+ LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64, xlen(target), info->misa);
+
+ return ERROR_OK;
+}
+
+static riscv_error_t handle_halt_routine(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+
+ scans_t *scans = scans_new(target, 256);
+
+ // Read all GPRs as fast as we can, because gdb is going to ask for them
+ // anyway. Reading them one at a time is much slower.
+
+ // Write the jump back to address 1.
+ scans_add_write_jump(scans, 1, false);
+ for (int reg = 1; reg < 32; reg++) {
+ if (reg == S0 || reg == S1) {
+ continue;
+ }
+
+ // Write store instruction.
+ scans_add_write_store(scans, 0, reg, SLOT0, true);
+
+ // Read value.
+ scans_add_read(scans, SLOT0, false);
+ }
+
+ // Write store of s0 at index 1.
+ scans_add_write_store(scans, 1, S0, SLOT0, false);
+ // Write jump at index 2.
+ scans_add_write_jump(scans, 2, false);
+
+ // Read S1 from debug RAM
+ scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
+ // Read value.
+ scans_add_read(scans, SLOT0, false);
+
+ // Read S0 from dscratch
+ unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
+ for (unsigned int i = 0; i < DIM(csr); i++) {
+ scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
+ scans_add_read(scans, SLOT0, false);
+ }
+
+ // Final read to get the last value out.
+ scans_add_read32(scans, 4, false);
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ unsigned int dbus_busy = 0;
+ unsigned int interrupt_set = 0;
+ unsigned result = 0;
+ uint64_t value = 0;
+ reg_cache_set(target, 0, 0);
+ // The first scan result is the result from something old we don't care
+ // about.
+ for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
+ dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
+ uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
+ info->addrbits);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug access failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ if (data & DMCONTROL_INTERRUPT) {
+ interrupt_set++;
+ break;
+ }
+ if (address == 4 || address == 5) {
+ unsigned int reg;
+ switch (result) {
+ case 0: reg = 1; break;
+ case 1: reg = 2; break;
+ case 2: reg = 3; break;
+ case 3: reg = 4; break;
+ case 4: reg = 5; break;
+ case 5: reg = 6; break;
+ case 6: reg = 7; break;
+ // S0
+ // S1
+ case 7: reg = 10; break;
+ case 8: reg = 11; break;
+ case 9: reg = 12; break;
+ case 10: reg = 13; break;
+ case 11: reg = 14; break;
+ case 12: reg = 15; break;
+ case 13: reg = 16; break;
+ case 14: reg = 17; break;
+ case 15: reg = 18; break;
+ case 16: reg = 19; break;
+ case 17: reg = 20; break;
+ case 18: reg = 21; break;
+ case 19: reg = 22; break;
+ case 20: reg = 23; break;
+ case 21: reg = 24; break;
+ case 22: reg = 25; break;
+ case 23: reg = 26; break;
+ case 24: reg = 27; break;
+ case 25: reg = 28; break;
+ case 26: reg = 29; break;
+ case 27: reg = 30; break;
+ case 28: reg = 31; break;
+ case 29: reg = S1; break;
+ case 30: reg = S0; break;
+ case 31: reg = CSR_DPC; break;
+ case 32: reg = CSR_DCSR; break;
+ default:
+ assert(0);
+ }
+ if (xlen(target) == 32) {
+ reg_cache_set(target, reg, data & 0xffffffff);
+ result++;
+ } else if (xlen(target) == 64) {
+ if (address == 4) {
+ value = data & 0xffffffff;
+ } else if (address == 5) {
+ reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
+ value = 0;
+ result++;
+ }
+ }
+ }
+ }
+
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ return RE_AGAIN;
+ }
+ if (interrupt_set) {
+ increase_interrupt_high_delay(target);
+ return RE_AGAIN;
+ }
+
+ // TODO: get rid of those 2 variables and talk to the cache directly.
+ info->dpc = reg_cache_get(target, CSR_DPC);
+ info->dcsr = reg_cache_get(target, CSR_DCSR);
+
+ scans = scans_delete(scans);
+
+ cache_invalidate(target);
+
+ return RE_OK;
+
+error:
+ scans = scans_delete(scans);
+ return RE_FAIL;
+}
+
+static int handle_halt(struct target *target, bool announce)
+{
+ riscv011_info_t *info = get_info(target);
+ target->state = TARGET_HALTED;
+
+ riscv_error_t re;
+ do {
+ re = handle_halt_routine(target);
+ } while (re == RE_AGAIN);
+ if (re != RE_OK) {
+ LOG_ERROR("handle_halt_routine failed");
+ return ERROR_FAIL;
+ }
+
+ int cause = get_field(info->dcsr, DCSR_CAUSE);
+ switch (cause) {
+ case DCSR_CAUSE_SWBP:
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ break;
+ case DCSR_CAUSE_HWBP:
+ target->debug_reason = DBG_REASON_WPTANDBKPT;
+ // If we halted because of a data trigger, gdb doesn't know to do
+ // the disable-breakpoints-step-enable-breakpoints dance.
+ info->need_strict_step = true;
+ break;
+ case DCSR_CAUSE_DEBUGINT:
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
+ case DCSR_CAUSE_STEP:
+ target->debug_reason = DBG_REASON_SINGLESTEP;
+ break;
+ case DCSR_CAUSE_HALT:
+ default:
+ LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
+ cause, info->dcsr);
+ }
+
+ if (info->never_halted) {
+ info->never_halted = false;
+
+ // Disable any hardware triggers that have dmode set. We can't have set
+ // them ourselves. Maybe they're left over from some killed debug
+ // session.
+ // Count the number of triggers while we're at it.
+
+ int result = maybe_read_tselect(target);
+ if (result != ERROR_OK)
+ return result;
+ for (info->trigger_count = 0; info->trigger_count < MAX_HWBPS; info->trigger_count++) {
+ write_csr(target, CSR_TSELECT, info->trigger_count);
+ uint64_t tselect_rb;
+ read_csr(target, &tselect_rb, CSR_TSELECT);
+ if (info->trigger_count != tselect_rb)
+ break;
+ uint64_t tdata1;
+ read_csr(target, &tdata1, CSR_TDATA1);
+ if ((tdata1 & MCONTROL_DMODE(xlen(target))) &&
+ (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD))) {
+ write_csr(target, CSR_TDATA1, 0);
+ }
+ }
+ }
+
+ if (announce) {
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ }
+
+ const char *cause_string[] = {
+ "none",
+ "software breakpoint",
+ "hardware trigger",
+ "debug interrupt",
+ "step",
+ "halt"
+ };
+ // This is logged to the user so that gdb will show it when a user types
+ // 'monitor reset init'. At that time gdb appears to have the pc cached
+ // still so if a user manually inspects the pc it will still have the old
+ // value.
+ LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
+
+ return ERROR_OK;
+}
+
+static int poll_target(struct target *target, bool announce)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // Inhibit debug logging during poll(), which isn't usually interesting and
+ // just fills up the screen/logs with clutter.
+ int old_debug_level = debug_level;
+ if (debug_level >= LOG_LVL_DEBUG) {
+ debug_level = LOG_LVL_INFO;
+ }
+ bits_t bits = read_bits(target);
+ debug_level = old_debug_level;
+
+ if (bits.haltnot && bits.interrupt) {
+ target->state = TARGET_DEBUG_RUNNING;
+ LOG_DEBUG("debug running");
+ } else if (bits.haltnot && !bits.interrupt) {
+ if (target->state != TARGET_HALTED) {
+ return handle_halt(target, announce);
+ }
+ } else if (!bits.haltnot && bits.interrupt) {
+ // Target is halting. There is no state for that, so don't change anything.
+ LOG_DEBUG("halting");
+ } else if (!bits.haltnot && !bits.interrupt) {
+ target->state = TARGET_RUNNING;
+ }
+
+ return ERROR_OK;
+}
+
+static int riscv011_poll(struct target *target)
+{
+ return poll_target(target, true);
+}
+
+static int riscv011_resume(struct target *target, int current, uint32_t address,
+ int handle_breakpoints, int debug_execution)
+{
+ riscv011_info_t *info = get_info(target);
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ if (!current) {
+ if (xlen(target) > 32) {
+ LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
+ xlen(target));
+ }
+ int result = register_write(target, REG_PC, address);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ if (info->need_strict_step || handle_breakpoints) {
+ int result = strict_step(target, false);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ return resume(target, debug_execution, false);
+}
+
+static int assert_reset(struct target *target)
+{
+ riscv011_info_t *info = get_info(target);
+ // TODO: Maybe what I implemented here is more like soft_reset_halt()?
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // The only assumption we can make is that the TAP was reset.
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ return ERROR_FAIL;
+ }
+
+ // Not sure what we should do when there are multiple cores.
+ // Here just reset the single hart we're talking to.
+ info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
+ DCSR_EBREAKU | DCSR_HALT;
+ if (target->reset_halt) {
+ info->dcsr |= DCSR_NDRESET;
+ } else {
+ info->dcsr |= DCSR_FULLRESET;
+ }
+ dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
+ dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
+ // We shouldn't actually need the jump because a reset should happen.
+ dram_write_jump(target, 2, false);
+ dram_write32(target, 4, info->dcsr, true);
+ cache_invalidate(target);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
+
+static int deassert_reset(struct target *target)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+ if (target->reset_halt) {
+ return wait_for_state(target, TARGET_HALTED);
+ } else {
+ return wait_for_state(target, TARGET_RUNNING);
+ }
+}
+
+static int read_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+ switch (size) {
+ case 1:
+ cache_set32(target, 1, lb(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 2:
+ cache_set32(target, 1, lh(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 4:
+ cache_set32(target, 1, lw(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
+ }
+ cache_set_jump(target, 3);
+ cache_write(target, CACHE_NO_READ, false);
+
+ riscv011_info_t *info = get_info(target);
+ const int max_batch_size = 256;
+ scans_t *scans = scans_new(target, max_batch_size);
+
+ uint32_t result_value = 0x777;
+ uint32_t i = 0;
+ while (i < count + 3) {
+ unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
+ scans_reset(scans);
+
+ for (unsigned int j = 0; j < batch_size; j++) {
+ if (i + j == count) {
+ // Just insert a read so we can scan out the last value.
+ scans_add_read32(scans, 4, false);
+ } else if (i + j >= count + 1) {
+ // And check for errors.
+ scans_add_read32(scans, info->dramsize-1, false);
+ } else {
+ // Write the next address and set interrupt.
+ uint32_t offset = size * (i + j);
+ scans_add_write32(scans, 4, address + offset, true);
+ }
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ int dbus_busy = 0;
+ int execute_busy = 0;
+ for (unsigned int j = 0; j < batch_size; j++) {
+ dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
+ DBUS_DATA_SIZE);
+ if (data & DMCONTROL_INTERRUPT) {
+ execute_busy++;
+ }
+ if (i + j == count + 2) {
+ result_value = data;
+ } else if (i + j > 1) {
+ uint32_t offset = size * (i + j - 2);
+ switch (size) {
+ case 1:
+ buffer[offset] = data;
+ break;
+ case 2:
+ buffer[offset] = data;
+ buffer[offset+1] = data >> 8;
+ break;
+ case 4:
+ buffer[offset] = data;
+ buffer[offset+1] = data >> 8;
+ buffer[offset+2] = data >> 16;
+ buffer[offset+3] = data >> 24;
+ break;
+ }
+ }
+ LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
+ }
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ }
+ if (execute_busy) {
+ increase_interrupt_high_delay(target);
+ }
+ if (dbus_busy || execute_busy) {
+ wait_for_debugint_clear(target, false);
+
+ // Retry.
+ LOG_INFO("Retrying memory read starting from 0x%x with more delays",
+ address + size * i);
+ } else {
+ i += batch_size;
+ }
+ }
+
+ if (result_value != 0) {
+ LOG_USER("Core got an exception (0x%x) while reading from 0x%x",
+ result_value, address + size * (count-1));
+ if (count > 1) {
+ LOG_USER("(It may have failed between 0x%x and 0x%x as well, but we "
+ "didn't check then.)",
+ address, address + size * (count-2) + size - 1);
+ }
+ goto error;
+ }
+
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_OK;
+
+error:
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_FAIL;
+}
+
+static int setup_write_memory(struct target *target, uint32_t size)
+{
+ switch (size) {
+ case 1:
+ cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sb(S0, T0, 0));
+ break;
+ case 2:
+ cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sh(S0, T0, 0));
+ break;
+ case 4:
+ cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sw(S0, T0, 0));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
+ }
+ cache_set32(target, 2, addi(T0, T0, size));
+ cache_set_jump(target, 3);
+ cache_write(target, 4, false);
+
+ return ERROR_OK;
+}
+
+static int write_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, const uint8_t *buffer)
+{
+ riscv011_info_t *info = get_info(target);
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // Set up the address.
+ cache_set_store(target, 0, T0, SLOT1);
+ cache_set_load(target, 1, T0, SLOT0);
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, address);
+ if (cache_write(target, 5, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint64_t t0 = cache_get(target, SLOT1);
+ LOG_DEBUG("t0 is 0x%" PRIx64, t0);
+
+ if (setup_write_memory(target, size) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ const int max_batch_size = 256;
+ scans_t *scans = scans_new(target, max_batch_size);
+
+ uint32_t result_value = 0x777;
+ uint32_t i = 0;
+ while (i < count + 2) {
+ unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
+ scans_reset(scans);
+
+ for (unsigned int j = 0; j < batch_size; j++) {
+ if (i + j >= count) {
+ // Check for an exception.
+ scans_add_read32(scans, info->dramsize-1, false);
+ } else {
+ // Write the next value and set interrupt.
+ uint32_t value;
+ uint32_t offset = size * (i + j);
+ switch (size) {
+ case 1:
+ value = buffer[offset];
+ break;
+ case 2:
+ value = buffer[offset] |
+ (buffer[offset+1] << 8);
+ break;
+ case 4:
+ value = buffer[offset] |
+ ((uint32_t) buffer[offset+1] << 8) |
+ ((uint32_t) buffer[offset+2] << 16) |
+ ((uint32_t) buffer[offset+3] << 24);
+ break;
+ default:
+ goto error;
+ }
+
+ scans_add_write32(scans, 4, value, true);
+ }
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ int dbus_busy = 0;
+ int execute_busy = 0;
+ for (unsigned int j = 0; j < batch_size; j++) {
+ dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
+ if (interrupt) {
+ execute_busy++;
+ }
+ if (i + j == count + 1) {
+ result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
+ }
+ }
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ }
+ if (execute_busy) {
+ increase_interrupt_high_delay(target);
+ }
+ if (dbus_busy || execute_busy) {
+ wait_for_debugint_clear(target, false);
+
+ // Retry.
+ // Set t0 back to what it should have been at the beginning of this
+ // batch.
+ LOG_INFO("Retrying memory write starting from 0x%x with more delays",
+ address + size * i);
+
+ cache_clean(target);
+
+ if (write_gpr(target, T0, address + size * i) != ERROR_OK) {
+ goto error;
+ }
+
+ if (setup_write_memory(target, size) != ERROR_OK) {
+ goto error;
+ }
+ } else {
+ i += batch_size;
+ }
+ }
+
+ if (result_value != 0) {
+ LOG_ERROR("Core got an exception (0x%x) while writing to 0x%x",
+ result_value, address + size * (count-1));
+ if (count > 1) {
+ LOG_ERROR("(It may have failed between 0x%x and 0x%x as well, but we "
+ "didn't check then.)",
+ address, address + size * (count-2) + size - 1);
+ }
+ goto error;
+ }
+
+ cache_clean(target);
+ return register_write(target, T0, t0);
+
+error:
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_FAIL;
+}
+
+static int arch_state(struct target *target)
+{
+ return ERROR_OK;
+}
+
+struct target_type riscv011_target =
+{
+ .name = "riscv",
+
+ .init_target = init_target,
+ .deinit_target = deinit_target,
+ .examine = examine,
+
+ /* poll current target status */
+ .poll = riscv011_poll,
+
+ .halt = halt,
+ .resume = riscv011_resume,
+ .step = step,
+
+ .assert_reset = assert_reset,
+ .deassert_reset = deassert_reset,
+
+ .read_memory = read_memory,
+ .write_memory = write_memory,
+
+ .add_breakpoint = add_breakpoint,
+ .remove_breakpoint = remove_breakpoint,
+
+ .add_watchpoint = add_watchpoint,
+ .remove_watchpoint = remove_watchpoint,
+
+ .arch_state = arch_state,
+};
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
new file mode 100644
index 0000000..efacbcc
--- /dev/null
+++ b/src/target/riscv/riscv-013.c
@@ -0,0 +1,2620 @@
+/*
+ * Support for RISC-V, debug version 0.13, which is currently (2/4/17) the
+ * latest draft.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <time.h>
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "target.h"
+#include "target/algorithm.h"
+#include "target_type.h"
+#include "log.h"
+#include "jtag/jtag.h"
+#include "register.h"
+#include "breakpoints.h"
+#include "helper/time_support.h"
+#include "riscv.h"
+#include "debug_defines.h"
+
+/**
+ * Since almost everything can be accomplish by scanning the dbus register, all
+ * functions here assume dbus is already selected. The exception are functions
+ * called directly by OpenOCD, which can't assume anything about what's
+ * currently in IR. They should set IR to dbus explicitly.
+ */
+
+/**
+ * Code structure
+ *
+ * At the bottom of the stack are the OpenOCD JTAG functions:
+ * jtag_add_[id]r_scan
+ * jtag_execute_query
+ * jtag_add_runtest
+ *
+ * There are a few functions to just instantly shift a register and get its
+ * value:
+ * dtmcontrol_scan
+ * idcode_scan
+ * dbus_scan
+ *
+ * Because doing one scan and waiting for the result is slow, most functions
+ * batch up a bunch of dbus writes and then execute them all at once. They use
+ * the scans "class" for this:
+ * scans_new
+ * scans_delete
+ * scans_execute
+ * scans_add_...
+ * Usually you new(), call a bunch of add functions, then execute() and look
+ * at the results by calling scans_get...()
+ *
+ * Optimized functions will directly use the scans class above, but slightly
+ * lazier code will use the cache functions that in turn use the scans
+ * functions:
+ * cache_get...
+ * cache_set...
+ * cache_write
+ * cache_set... update a local structure, which is then synced to the target
+ * with cache_write(). Only Debug RAM words that are actually changed are sent
+ * to the target. Afterwards use cache_get... to read results.
+ */
+
+#define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
+#define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
+
+#define DIM(x) (sizeof(x)/sizeof(*x))
+
+// Constants for legacy SiFive hardware breakpoints.
+#define CSR_BPCONTROL_X (1<<0)
+#define CSR_BPCONTROL_W (1<<1)
+#define CSR_BPCONTROL_R (1<<2)
+#define CSR_BPCONTROL_U (1<<3)
+#define CSR_BPCONTROL_S (1<<4)
+#define CSR_BPCONTROL_H (1<<5)
+#define CSR_BPCONTROL_M (1<<6)
+#define CSR_BPCONTROL_BPMATCH (0xf<<7)
+#define CSR_BPCONTROL_BPACTION (0xff<<11)
+
+#define DEBUG_ROM_START 0x800
+#define DEBUG_ROM_RESUME (DEBUG_ROM_START + 4)
+#define DEBUG_ROM_EXCEPTION (DEBUG_ROM_START + 8)
+#define DEBUG_RAM_START 0x400
+
+#define SETHALTNOT 0x10c
+
+/*** JTAG registers. ***/
+
+#define DBUS 0x11
+#define DBUS_OP_START 0
+#define DBUS_OP_SIZE 2
+typedef enum {
+ DBUS_OP_NOP = 0,
+ DBUS_OP_READ = 1,
+ DBUS_OP_WRITE = 2
+} dbus_op_t;
+typedef enum {
+ DBUS_STATUS_SUCCESS = 0,
+ DBUS_STATUS_FAILED = 2,
+ DBUS_STATUS_BUSY = 3
+} dbus_status_t;
+#define DBUS_DATA_START 2
+#define DBUS_DATA_SIZE 32
+#define DBUS_ADDRESS_START 34
+
+typedef enum {
+ RE_OK,
+ RE_FAIL,
+ RE_AGAIN
+} riscv_error_t;
+
+typedef enum slot {
+ SLOT0,
+ SLOT1,
+ SLOT_LAST,
+} slot_t;
+
+/*** Debug Bus registers. ***/
+
+#define DMCONTROL 0x10
+#define DMCONTROL_INTERRUPT (((uint64_t)1)<<33)
+#define DMCONTROL_HALTNOT (((uint64_t)1)<<32)
+#define DMCONTROL_BUSERROR (7<<19)
+#define DMCONTROL_SERIAL (3<<16)
+#define DMCONTROL_AUTOINCREMENT (1<<15)
+#define DMCONTROL_ACCESS (7<<12)
+#define DMCONTROL_HARTID (0x3ff<<2)
+#define DMCONTROL_NDRESET (1<<1)
+#define DMCONTROL_FULLRESET 1
+
+/*** Info about the core being debugged. ***/
+
+#define DBUS_ADDRESS_UNKNOWN 0xffff
+#define WALL_CLOCK_TIMEOUT 2
+
+// gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
+// its source tree. We must interpret the numbers the same here.
+enum {
+ REG_XPR0 = 0,
+ REG_XPR31 = 31,
+ REG_PC = 32,
+ REG_FPR0 = 33,
+ REG_FPR31 = 64,
+ REG_CSR0 = 65,
+ REG_MSTATUS = CSR_MSTATUS + REG_CSR0,
+ REG_CSR4095 = 4160,
+ REG_PRIV = 4161,
+ REG_COUNT
+};
+
+#define MAX_HWBPS 16
+#define DRAM_CACHE_SIZE 16
+
+struct trigger {
+ uint64_t address;
+ uint32_t length;
+ uint64_t mask;
+ uint64_t value;
+ bool read, write, execute;
+ int unique_id;
+};
+
+struct memory_cache_line {
+ uint32_t data;
+ bool valid;
+ bool dirty;
+};
+
+typedef struct {
+ /* Number of address bits in the dbus register. */
+ unsigned abits;
+ /* Number of abstract command data registers. */
+ unsigned datacount;
+ /* Number of words in the Program Buffer. */
+ unsigned progsize;
+ /* Number of Program Buffer registers. */
+ /* Number of words in Debug RAM. */
+ unsigned int dramsize; // TODO: remove
+ uint64_t dcsr;
+ uint64_t dpc;
+ uint64_t misa;
+ uint64_t tselect;
+ bool tselect_dirty;
+ /* The value that mstatus actually has on the target right now. This is not
+ * the value we present to the user. That one may be stored in the
+ * reg_cache. */
+ uint64_t mstatus_actual;
+
+ struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
+
+ /* Single buffer that contains all register names, instead of calling
+ * malloc for each register. Needs to be freed when reg_list is freed. */
+ char *reg_names;
+ /* Single buffer that contains all register values. */
+ void *reg_values;
+
+ // For each physical trigger, contains -1 if the hwbp is available, or the
+ // unique_id of the breakpoint/watchpoint that is using it.
+ int trigger_unique_id[MAX_HWBPS];
+
+ unsigned int trigger_count;
+
+ // Number of run-test/idle cycles the target requests we do after each dbus
+ // access.
+ unsigned int dtmcontrol_idle;
+
+ // This value is incremented every time a dbus access comes back as "busy".
+ // It's used to determine how many run-test/idle cycles to feed the target
+ // in between accesses.
+ unsigned int dbus_busy_delay;
+
+ // This value is incremented every time we read the debug interrupt as
+ // high. It's used to add extra run-test/idle cycles after setting debug
+ // interrupt high, so ideally we never have to perform a whole extra scan
+ // before the interrupt is cleared.
+ unsigned int interrupt_high_delay;
+
+ bool need_strict_step;
+ bool never_halted;
+} riscv013_info_t;
+
+typedef struct {
+ bool haltnot;
+ bool interrupt;
+} bits_t;
+
+/*** Necessary prototypes. ***/
+
+static int poll_target(struct target *target, bool announce);
+static int riscv013_poll(struct target *target);
+static int register_get(struct reg *reg);
+
+/*** Utility functions. ***/
+
+#define DEBUG_LENGTH 264
+
+static riscv013_info_t *get_info(const struct target *target)
+{
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ return (riscv013_info_t *) info->version_specific;
+}
+
+static unsigned int slot_offset(const struct target *target, slot_t slot)
+{
+ riscv013_info_t *info = get_info(target);
+ switch (xlen(target)) {
+ case 32:
+ switch (slot) {
+ case SLOT0: return 4;
+ case SLOT1: return 5;
+ case SLOT_LAST: return info->dramsize-1;
+ }
+ case 64:
+ switch (slot) {
+ case SLOT0: return 4;
+ case SLOT1: return 6;
+ case SLOT_LAST: return info->dramsize-2;
+ }
+ }
+ LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
+ xlen(target), slot);
+ assert(0);
+}
+
+static uint32_t load_slot(const struct target *target, unsigned int dest,
+ slot_t slot)
+{
+ unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ return load(target, dest, ZERO, offset);
+}
+
+static uint32_t store_slot(const struct target *target, unsigned int src,
+ slot_t slot)
+{
+ unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ return store(target, src, ZERO, offset);
+}
+
+static uint16_t dram_address(unsigned int index)
+{
+ if (index < 0x10)
+ return index;
+ else
+ return 0x40 + index - 0x10;
+}
+
+static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
+{
+ struct scan_field field;
+ uint8_t in_value[4];
+ uint8_t out_value[4];
+
+ buf_set_u32(out_value, 0, 32, out);
+
+ jtag_add_ir_scan(target->tap, &select_dtmcontrol, TAP_IDLE);
+
+ field.num_bits = 32;
+ field.out_value = out_value;
+ field.in_value = in_value;
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ /* Always return to dbus. */
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ uint32_t in = buf_get_u32(field.in_value, 0, 32);
+ LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
+
+ return in;
+}
+
+static uint32_t idcode_scan(struct target *target)
+{
+ struct scan_field field;
+ uint8_t in_value[4];
+
+ jtag_add_ir_scan(target->tap, &select_idcode, TAP_IDLE);
+
+ field.num_bits = 32;
+ field.out_value = NULL;
+ field.in_value = in_value;
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ /* Always return to dbus. */
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ uint32_t in = buf_get_u32(field.in_value, 0, 32);
+ LOG_DEBUG("IDCODE: 0x0 -> 0x%x", in);
+
+ return in;
+}
+
+static void increase_dbus_busy_delay(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
+ LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
+ info->dtmcontrol_idle, info->dbus_busy_delay,
+ info->interrupt_high_delay);
+
+ dtmcontrol_scan(target, DTM_DTMCONTROL_DBUSRESET);
+}
+
+static void increase_interrupt_high_delay(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
+ LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
+ info->dtmcontrol_idle, info->dbus_busy_delay,
+ info->interrupt_high_delay);
+}
+
+static void add_dbus_scan(const struct target *target, struct scan_field *field,
+ uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
+ uint16_t address, uint64_t data)
+{
+ riscv013_info_t *info = get_info(target);
+
+ field->num_bits = info->abits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
+ field->in_value = in_value;
+ field->out_value = out_value;
+
+ buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
+ buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
+ buf_set_u64(out_value, DBUS_ADDRESS_START, info->abits, address);
+
+ jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
+
+ int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
+ if (data & DMCONTROL_INTERRUPT) {
+ idle_count += info->interrupt_high_delay;
+ }
+
+ if (idle_count) {
+ jtag_add_runtest(idle_count, TAP_IDLE);
+ }
+}
+
+static void dump_field(const struct scan_field *field)
+{
+ static const char *op_string[] = {"nop", "r", "w", "?"};
+ static const char *status_string[] = {"+", "?", "F", "b"};
+
+ if (debug_level < LOG_LVL_DEBUG)
+ return;
+
+ uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
+ unsigned int out_op = get_field(out, DTM_DBUS_OP);
+ unsigned int out_data = get_field(out, DTM_DBUS_DATA);
+ unsigned int out_address = out >> DTM_DBUS_ADDRESS_OFFSET;
+ uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
+ unsigned int in_op = get_field(in, DTM_DBUS_OP);
+ unsigned int in_data = get_field(in, DTM_DBUS_DATA);
+ unsigned int in_address = in >> DTM_DBUS_ADDRESS_OFFSET;
+
+ log_printf_lf(LOG_LVL_DEBUG,
+ __FILE__, __LINE__, "scan",
+ "%db %s %08x @%02x -> %s %08x @%02x",
+ field->num_bits,
+ op_string[out_op], out_data, out_address,
+ status_string[in_op], in_data, in_address);
+}
+
+static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
+ uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
+{
+ riscv013_info_t *info = get_info(target);
+ uint8_t in[8] = {0};
+ uint8_t out[8];
+ struct scan_field field = {
+ .num_bits = info->abits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
+ .out_value = out,
+ .in_value = in
+ };
+
+ assert(info->abits != 0);
+
+ buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
+ buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
+ buf_set_u64(out, DBUS_ADDRESS_START, info->abits, address_out);
+
+ /* Assume dbus is already selected. */
+ jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+
+ int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
+
+ if (idle_count) {
+ jtag_add_runtest(idle_count, TAP_IDLE);
+ }
+
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("dbus_scan failed jtag scan");
+ return retval;
+ }
+
+ if (data_in) {
+ *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
+ }
+
+ if (address_in) {
+ *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->abits);
+ }
+
+ dump_field(&field);
+
+ return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
+}
+
+static uint64_t dbus_read(struct target *target, uint16_t address)
+{
+ uint64_t value;
+ dbus_status_t status;
+ uint16_t address_in;
+
+ unsigned i = 0;
+ do {
+ status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
+ if (status == DBUS_STATUS_BUSY) {
+ increase_dbus_busy_delay(target);
+ }
+ } while (((status != DBUS_STATUS_SUCCESS) || (address_in != address)) &&
+ i++ < 256);
+
+ if (status != DBUS_STATUS_SUCCESS) {
+ LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n",
+ address, value, status);
+ }
+
+ return value;
+}
+
+static void dbus_write(struct target *target, uint16_t address, uint64_t value)
+{
+ dbus_status_t status = DBUS_STATUS_BUSY;
+ unsigned i = 0;
+ while (status == DBUS_STATUS_BUSY && i++ < 256) {
+ status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
+ if (status == DBUS_STATUS_BUSY) {
+ increase_dbus_busy_delay(target);
+ }
+ }
+ if (status != DBUS_STATUS_SUCCESS) {
+ LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
+ }
+}
+
+/*** scans "class" ***/
+
+typedef struct {
+ // Number of scans that space is reserved for.
+ unsigned int scan_count;
+ // Size reserved in memory for each scan, in bytes.
+ unsigned int scan_size;
+ unsigned int next_scan;
+ uint8_t *in;
+ uint8_t *out;
+ struct scan_field *field;
+ const struct target *target;
+} scans_t;
+
+static scans_t *scans_new(struct target *target, unsigned int scan_count)
+{
+ scans_t *scans = malloc(sizeof(scans_t));
+ scans->scan_count = scan_count;
+ // This code also gets called before xlen is detected.
+ if (xlen(target))
+ scans->scan_size = 2 + xlen(target) / 8;
+ else
+ scans->scan_size = 2 + 128 / 8;
+ scans->next_scan = 0;
+ scans->in = calloc(scans->scan_size, scans->scan_count);
+ scans->out = calloc(scans->scan_size, scans->scan_count);
+ scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
+ scans->target = target;
+ return scans;
+}
+
+static scans_t *scans_delete(scans_t *scans)
+{
+ assert(scans);
+ free(scans->field);
+ free(scans->out);
+ free(scans->in);
+ free(scans);
+ return NULL;
+}
+
+static void scans_reset(scans_t *scans)
+{
+ scans->next_scan = 0;
+}
+
+static void scans_dump(scans_t *scans)
+{
+ for (unsigned int i = 0; i < scans->next_scan; i++) {
+ dump_field(&scans->field[i]);
+ }
+}
+
+static int scans_execute(scans_t *scans)
+{
+ int retval = jtag_execute_queue();
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed jtag scan: %d", retval);
+ return retval;
+ }
+
+ scans_dump(scans);
+
+ return ERROR_OK;
+}
+
+/** Add a 32-bit dbus write to the scans structure. */
+static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
+ bool set_interrupt)
+{
+ const unsigned int i = scans->next_scan;
+ int data_offset = scans->scan_size * i;
+ add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
+ scans->in + data_offset, DBUS_OP_WRITE, address,
+ (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
+ scans->next_scan++;
+ assert(scans->next_scan <= scans->scan_count);
+}
+
+/** Add a 32-bit dbus write for an instruction that jumps to the beginning of
+ * debug RAM. */
+static void scans_add_write_jump(scans_t *scans, uint16_t address,
+ bool set_interrupt)
+{
+ scans_add_write32(scans, address,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus write for an instruction that loads from the indicated
+ * slot. */
+static void scans_add_write_load(scans_t *scans, uint16_t address,
+ unsigned int reg, slot_t slot, bool set_interrupt)
+{
+ scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus write for an instruction that stores to the indicated
+ * slot. */
+static void scans_add_write_store(scans_t *scans, uint16_t address,
+ unsigned int reg, slot_t slot, bool set_interrupt)
+{
+ scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
+ set_interrupt);
+}
+
+/** Add a 32-bit dbus read. */
+static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
+{
+ assert(scans->next_scan < scans->scan_count);
+ const unsigned int i = scans->next_scan;
+ int data_offset = scans->scan_size * i;
+ add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
+ scans->in + data_offset, DBUS_OP_READ, address,
+ (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
+ scans->next_scan++;
+}
+
+/** Add one or more scans to read the indicated slot. */
+static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
+{
+ const struct target *target = scans->target;
+ switch (xlen(target)) {
+ case 32:
+ scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
+ break;
+ case 64:
+ scans_add_read32(scans, slot_offset(target, slot), false);
+ scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
+ break;
+ }
+}
+
+static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
+ unsigned first, unsigned num)
+{
+ return buf_get_u32(scans->in + scans->scan_size * index, first, num);
+}
+
+static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
+ unsigned first, unsigned num)
+{
+ return buf_get_u64(scans->in + scans->scan_size * index, first, num);
+}
+
+/*** end of scans class ***/
+
+static uint32_t dram_read32(struct target *target, unsigned int index)
+{
+ uint16_t address = dram_address(index);
+ uint32_t value = dbus_read(target, address);
+ return value;
+}
+
+static void dram_write32(struct target *target, unsigned int index, uint32_t value,
+ bool set_interrupt)
+{
+ uint64_t dbus_value = DMCONTROL_HALTNOT | value;
+ if (set_interrupt)
+ dbus_value |= DMCONTROL_INTERRUPT;
+ dbus_write(target, dram_address(index), dbus_value);
+}
+
+/** Read the haltnot and interrupt bits. */
+static bits_t read_bits(struct target *target)
+{
+ uint64_t value;
+ dbus_status_t status;
+ uint16_t address_in;
+ riscv013_info_t *info = get_info(target);
+
+ bits_t err_result = {
+ .haltnot = 0,
+ .interrupt = 0
+ };
+
+ do {
+ unsigned i = 0;
+ do {
+ status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
+ if (status == DBUS_STATUS_BUSY) {
+ if (address_in == (1<<info->abits) - 1 &&
+ value == (1ULL<<DBUS_DATA_SIZE) - 1) {
+ LOG_ERROR("TDO seems to be stuck high.");
+ return err_result;
+ }
+ increase_dbus_busy_delay(target);
+ }
+ } while (status == DBUS_STATUS_BUSY && i++ < 256);
+
+ if (i >= 256) {
+ LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
+ return err_result;
+ }
+ } while (address_in > 0x10 && address_in != DMCONTROL);
+
+ bits_t result = {
+ .haltnot = get_field(value, DMCONTROL_HALTNOT),
+ .interrupt = get_field(value, DMCONTROL_INTERRUPT)
+ };
+ return result;
+}
+
+static int wait_for_debugint_clear(struct target *target, bool ignore_first)
+{
+ time_t start = time(NULL);
+ if (ignore_first) {
+ // Throw away the results of the first read, since they'll contain the
+ // result of the read that happened just before debugint was set.
+ // (Assuming the last scan before calling this function was one that
+ // sets debugint.)
+ read_bits(target);
+ }
+ while (1) {
+ bits_t bits = read_bits(target);
+ if (!bits.interrupt) {
+ return ERROR_OK;
+ }
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for debug int to clear.");
+ return ERROR_FAIL;
+ }
+ }
+}
+
+static int dram_check32(struct target *target, unsigned int index,
+ uint32_t expected)
+{
+ uint16_t address = dram_address(index);
+ uint32_t actual = dbus_read(target, address);
+ if (expected != actual) {
+ LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
+ expected, index, actual);
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static void cache_set32(struct target *target, unsigned int index, uint32_t data)
+{
+ riscv013_info_t *info = get_info(target);
+ if (info->dram_cache[index].valid &&
+ info->dram_cache[index].data == data) {
+ // This is already preset on the target.
+ LOG_DEBUG("cache[0x%x] = 0x%x (hit)", index, data);
+ return;
+ }
+ LOG_DEBUG("cache[0x%x] = 0x%x", index, data);
+ info->dram_cache[index].data = data;
+ info->dram_cache[index].valid = true;
+ info->dram_cache[index].dirty = true;
+}
+
+static void cache_set(struct target *target, slot_t slot, uint64_t data)
+{
+ unsigned int offset = slot_offset(target, slot);
+ cache_set32(target, offset, data);
+ if (xlen(target) > 32) {
+ cache_set32(target, offset + 1, data >> 32);
+ }
+}
+
+static void cache_set_jump(struct target *target, unsigned int index)
+{
+ cache_set32(target, index,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
+}
+
+static void cache_set_load(struct target *target, unsigned int index,
+ unsigned int reg, slot_t slot)
+{
+ uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ cache_set32(target, index, load(target, reg, ZERO, offset));
+}
+
+static void cache_set_store(struct target *target, unsigned int index,
+ unsigned int reg, slot_t slot)
+{
+ uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
+ cache_set32(target, index, store(target, reg, ZERO, offset));
+}
+
+static void dump_debug_ram(struct target *target)
+{
+ for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
+ uint32_t value = dram_read32(target, i);
+ LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
+ }
+}
+
+/* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
+static void cache_invalidate(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ info->dram_cache[i].valid = false;
+ info->dram_cache[i].dirty = false;
+ }
+}
+
+/* Called by cache_write() after the program has run. Also call this if you're
+ * running programs without calling cache_write(). */
+static void cache_clean(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (i >= 4) {
+ info->dram_cache[i].valid = false;
+ }
+ info->dram_cache[i].dirty = false;
+ }
+}
+
+static int cache_check(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ int error = 0;
+
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
+ if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK) {
+ error++;
+ }
+ }
+ }
+
+ if (error) {
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+/** Write cache to the target, and optionally run the program.
+ * Then read the value at address into the cache, assuming address < 128. */
+#define CACHE_NO_READ 128
+static int cache_write(struct target *target, unsigned int address, bool run)
+{
+ LOG_DEBUG("enter");
+ riscv013_info_t *info = get_info(target);
+ scans_t *scans = scans_new(target, info->dramsize + 2);
+
+ unsigned int last = info->dramsize;
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].dirty) {
+ last = i;
+ }
+ }
+
+ if (last == info->dramsize) {
+ // Nothing needs to be written to RAM.
+ dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT);
+
+ } else {
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (info->dram_cache[i].dirty) {
+ bool set_interrupt = (i == last && run);
+ scans_add_write32(scans, i, info->dram_cache[i].data,
+ set_interrupt);
+ }
+ }
+ }
+
+ if (run || address < CACHE_NO_READ) {
+ // Throw away the results of the first read, since it'll contain the
+ // result of the read that happened just before debugint was set.
+ scans_add_read32(scans, address, false);
+
+ // This scan contains the results of the read the caller requested, as
+ // well as an interrupt bit worth looking at.
+ scans_add_read32(scans, address, false);
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed.");
+ return retval;
+ }
+
+ int errors = 0;
+ for (unsigned int i = 0; i < scans->next_scan; i++) {
+ dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ return ERROR_FAIL;
+ case DBUS_STATUS_BUSY:
+ errors++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ }
+
+ if (errors) {
+ increase_dbus_busy_delay(target);
+
+ // Try again, using the slow careful code.
+ // Write all RAM, just to be extra cautious.
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ if (i == last && run) {
+ dram_write32(target, last, info->dram_cache[last].data, true);
+ } else {
+ dram_write32(target, i, info->dram_cache[i].data, false);
+ }
+ info->dram_cache[i].dirty = false;
+ }
+ if (run) {
+ cache_clean(target);
+ }
+
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+
+ } else {
+ if (run) {
+ cache_clean(target);
+ } else {
+ for (unsigned int i = 0; i < info->dramsize; i++) {
+ info->dram_cache[i].dirty = false;
+ }
+ }
+
+ if (run || address < CACHE_NO_READ) {
+ int interrupt = scans_get_u32(scans, scans->next_scan-1,
+ DBUS_DATA_START + 33, 1);
+ if (interrupt) {
+ increase_interrupt_high_delay(target);
+ // Slow path wait for it to clear.
+ if (wait_for_debugint_clear(target, false) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+ } else {
+ // We read a useful value in that last scan.
+ unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
+ DBUS_ADDRESS_START, info->abits);
+ if (read_addr != address) {
+ LOG_INFO("Got data from 0x%x but expected it from 0x%x",
+ read_addr, address);
+ }
+ info->dram_cache[read_addr].data =
+ scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
+ info->dram_cache[read_addr].valid = true;
+ }
+ }
+ }
+
+ scans_delete(scans);
+ LOG_DEBUG("exit");
+
+ return ERROR_OK;
+}
+
+static uint32_t cache_get32(struct target *target, unsigned int address)
+{
+ riscv013_info_t *info = get_info(target);
+ if (!info->dram_cache[address].valid) {
+ info->dram_cache[address].data = dram_read32(target, address);
+ info->dram_cache[address].valid = true;
+ }
+ return info->dram_cache[address].data;
+}
+
+static uint64_t cache_get(struct target *target, slot_t slot)
+{
+ unsigned int offset = slot_offset(target, slot);
+ uint64_t value = cache_get32(target, offset);
+ if (xlen(target) > 32) {
+ value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
+ }
+ return value;
+}
+
+/* Write instruction that jumps from the specified word in Debug RAM to resume
+ * in Debug ROM. */
+static void dram_write_jump(struct target *target, unsigned int index,
+ bool set_interrupt)
+{
+ dram_write32(target, index,
+ jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
+ set_interrupt);
+}
+
+static int wait_for_state(struct target *target, enum target_state state)
+{
+ time_t start = time(NULL);
+ while (1) {
+ int result = riscv013_poll(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ if (target->state == state) {
+ return ERROR_OK;
+ }
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for state %d.", state);
+ return ERROR_FAIL;
+ }
+ }
+}
+
+static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
+{
+ cache_set32(target, 0, csrr(S0, csr));
+ cache_set_store(target, 1, S0, SLOT0);
+ cache_set_jump(target, 2);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ *value = cache_get(target, SLOT0);
+ LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
+
+ return ERROR_OK;
+}
+
+static int write_csr(struct target *target, uint32_t csr, uint64_t value)
+{
+ LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, csr));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
+{
+ cache_set_load(target, 0, gpr, SLOT0);
+ cache_set_jump(target, 1);
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static int maybe_read_tselect(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+
+ if (info->tselect_dirty) {
+ int result = read_csr(target, &info->tselect, CSR_TSELECT);
+ if (result != ERROR_OK)
+ return result;
+ info->tselect_dirty = false;
+ }
+
+ return ERROR_OK;
+}
+
+static int maybe_write_tselect(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+
+ if (!info->tselect_dirty) {
+ int result = write_csr(target, CSR_TSELECT, info->tselect);
+ if (result != ERROR_OK)
+ return result;
+ info->tselect_dirty = true;
+ }
+
+ return ERROR_OK;
+}
+
+static int execute_resume(struct target *target, bool step)
+{
+ riscv013_info_t *info = get_info(target);
+
+ LOG_DEBUG("step=%d", step);
+
+ maybe_write_tselect(target);
+
+ // TODO: check if dpc is dirty (which also is true if an exception was hit
+ // at any time)
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_DPC));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, info->dpc);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
+ if (mstatus_reg->valid) {
+ uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, xlen(target));
+ if (mstatus_user != info->mstatus_actual) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, mstatus_user);
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+ }
+ }
+
+ info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
+ info->dcsr &= ~DCSR_HALT;
+
+ if (step) {
+ info->dcsr |= DCSR_STEP;
+ } else {
+ info->dcsr &= ~DCSR_STEP;
+ }
+
+ dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
+ dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
+ dram_write32(target, 2, fence_i(), false);
+ dram_write_jump(target, 3, false);
+
+ // Write DCSR value, set interrupt and clear haltnot.
+ uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
+ dbus_write(target, dram_address(4), dbus_value);
+
+ cache_invalidate(target);
+
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ return ERROR_FAIL;
+ }
+
+ target->state = TARGET_RUNNING;
+ register_cache_invalidate(target->reg_cache);
+
+ return ERROR_OK;
+}
+
+// Execute a step, and wait for reentry into Debug Mode.
+static int full_step(struct target *target, bool announce)
+{
+ int result = execute_resume(target, true);
+ if (result != ERROR_OK)
+ return result;
+ time_t start = time(NULL);
+ while (1) {
+ result = poll_target(target, announce);
+ if (result != ERROR_OK)
+ return result;
+ if (target->state != TARGET_DEBUG_RUNNING)
+ break;
+ if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
+ LOG_ERROR("Timed out waiting for step to complete.");
+ return ERROR_FAIL;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int resume(struct target *target, int debug_execution, bool step)
+{
+ if (debug_execution) {
+ LOG_ERROR("TODO: debug_execution is true");
+ return ERROR_FAIL;
+ }
+
+ return execute_resume(target, step);
+}
+
+/** Update register sizes based on xlen. */
+static void update_reg_list(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ if (info->reg_values) {
+ free(info->reg_values);
+ }
+ info->reg_values = malloc(REG_COUNT * xlen(target) / 4);
+
+ for (unsigned int i = 0; i < REG_COUNT; i++) {
+ struct reg *r = &target->reg_cache->reg_list[i];
+ r->value = info->reg_values + i * xlen(target) / 4;
+ if (r->dirty) {
+ LOG_ERROR("Register %d was dirty. Its value is lost.", i);
+ }
+ if (i == REG_PRIV) {
+ r->size = 8;
+ } else {
+ r->size = xlen(target);
+ }
+ r->valid = false;
+ }
+}
+
+static uint64_t reg_cache_get(struct target *target, unsigned int number)
+{
+ struct reg *r = &target->reg_cache->reg_list[number];
+ if (!r->valid) {
+ LOG_ERROR("Register cache entry for %d is invalid!", number);
+ assert(r->valid);
+ }
+ uint64_t value = buf_get_u64(r->value, 0, r->size);
+ LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
+ return value;
+}
+
+static void reg_cache_set(struct target *target, unsigned int number,
+ uint64_t value)
+{
+ struct reg *r = &target->reg_cache->reg_list[number];
+ LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
+ r->valid = true;
+ buf_set_u64(r->value, 0, r->size, value);
+}
+
+static int update_mstatus_actual(struct target *target)
+{
+ struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
+ if (mstatus_reg->valid) {
+ // We previously made it valid.
+ return ERROR_OK;
+ }
+
+ // Force reading the register. In that process mstatus_actual will be
+ // updated.
+ return register_get(&target->reg_cache->reg_list[REG_MSTATUS]);
+}
+
+/*** OpenOCD target functions. ***/
+
+static int register_get(struct reg *reg)
+{
+ struct target *target = (struct target *) reg->arch_info;
+ riscv013_info_t *info = get_info(target);
+
+ maybe_write_tselect(target);
+
+ if (reg->number <= REG_XPR31) {
+ buf_set_u64(reg->value, 0, xlen(target), reg_cache_get(target, reg->number));
+ LOG_DEBUG("%s=0x%" PRIx64, reg->name, reg_cache_get(target, reg->number));
+ return ERROR_OK;
+ } else if (reg->number == REG_PC) {
+ buf_set_u32(reg->value, 0, 32, info->dpc);
+ reg->valid = true;
+ LOG_DEBUG("%s=0x%" PRIx64 " (cached)", reg->name, info->dpc);
+ return ERROR_OK;
+ } else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
+ int result = update_mstatus_actual(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ unsigned i = 0;
+ if ((info->mstatus_actual & MSTATUS_FS) == 0) {
+ info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
+ cache_set_load(target, i++, S0, SLOT1);
+ cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
+ cache_set(target, SLOT1, info->mstatus_actual);
+ }
+
+ if (xlen(target) == 32) {
+ cache_set32(target, i++, fsw(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ } else {
+ cache_set32(target, i++, fsd(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ }
+ cache_set_jump(target, i++);
+ } else if (reg->number >= REG_CSR0 && reg->number <= REG_CSR4095) {
+ cache_set32(target, 0, csrr(S0, reg->number - REG_CSR0));
+ cache_set_store(target, 1, S0, SLOT0);
+ cache_set_jump(target, 2);
+ } else if (reg->number == REG_PRIV) {
+ buf_set_u64(reg->value, 0, 8, get_field(info->dcsr, DCSR_PRV));
+ LOG_DEBUG("%s=%d (cached)", reg->name,
+ (int) get_field(info->dcsr, DCSR_PRV));
+ return ERROR_OK;
+ } else {
+ LOG_ERROR("Don't know how to read register %d (%s)", reg->number, reg->name);
+ return ERROR_FAIL;
+ }
+
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ if (exception) {
+ LOG_ERROR("Got exception 0x%x when reading register %d", exception,
+ reg->number);
+ buf_set_u64(reg->value, 0, xlen(target), ~0);
+ return ERROR_FAIL;
+ }
+
+ uint64_t value = cache_get(target, SLOT0);
+ LOG_DEBUG("%s=0x%" PRIx64, reg->name, value);
+ buf_set_u64(reg->value, 0, xlen(target), value);
+
+ if (reg->number == REG_MSTATUS) {
+ info->mstatus_actual = value;
+ reg->valid = true;
+ }
+
+ return ERROR_OK;
+}
+
+static int register_write(struct target *target, unsigned int number,
+ uint64_t value)
+{
+ riscv013_info_t *info = get_info(target);
+
+ maybe_write_tselect(target);
+
+ if (number == S0) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
+ cache_set_jump(target, 2);
+ } else if (number == S1) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set_store(target, 1, S0, SLOT_LAST);
+ cache_set_jump(target, 2);
+ } else if (number <= REG_XPR31) {
+ cache_set_load(target, 0, number - REG_XPR0, SLOT0);
+ cache_set_jump(target, 1);
+ } else if (number == REG_PC) {
+ info->dpc = value;
+ return ERROR_OK;
+ } else if (number >= REG_FPR0 && number <= REG_FPR31) {
+ int result = update_mstatus_actual(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ unsigned i = 0;
+ if ((info->mstatus_actual & MSTATUS_FS) == 0) {
+ info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
+ cache_set_load(target, i++, S0, SLOT1);
+ cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
+ cache_set(target, SLOT1, info->mstatus_actual);
+ }
+
+ if (xlen(target) == 32) {
+ cache_set32(target, i++, flw(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ } else {
+ cache_set32(target, i++, fld(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
+ }
+ cache_set_jump(target, i++);
+ } else if (number >= REG_CSR0 && number <= REG_CSR4095) {
+ cache_set_load(target, 0, S0, SLOT0);
+ cache_set32(target, 1, csrw(S0, number - REG_CSR0));
+ cache_set_jump(target, 2);
+
+ if (number == REG_MSTATUS) {
+ info->mstatus_actual = value;
+ }
+ } else if (number == REG_PRIV) {
+ info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
+ return ERROR_OK;
+ } else {
+ LOG_ERROR("Don't know how to write register %d", number);
+ return ERROR_FAIL;
+ }
+
+ cache_set(target, SLOT0, value);
+ if (cache_write(target, info->dramsize - 1, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ if (exception) {
+ LOG_ERROR("Got exception 0x%x when writing register %d", exception,
+ number);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int register_set(struct reg *reg, uint8_t *buf)
+{
+ struct target *target = (struct target *) reg->arch_info;
+
+ uint64_t value = buf_get_u64(buf, 0, xlen(target));
+
+ LOG_DEBUG("write 0x%" PRIx64 " to %s", value, reg->name);
+ struct reg *r = &target->reg_cache->reg_list[reg->number];
+ r->valid = true;
+ memcpy(r->value, buf, (r->size + 7) / 8);
+
+ return register_write(target, reg->number, value);
+}
+
+static struct reg_arch_type riscv_reg_arch_type = {
+ .get = register_get,
+ .set = register_set
+};
+
+static int halt(struct target *target)
+{
+ LOG_DEBUG("riscv_halt()");
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
+ cache_set32(target, 1, csrr(S0, CSR_MHARTID));
+ cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
+ cache_set_jump(target, 3);
+
+ if (cache_write(target, 4, true) != ERROR_OK) {
+ LOG_ERROR("cache_write() failed.");
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int init_target(struct command_context *cmd_ctx,
+ struct target *target)
+{
+ LOG_DEBUG("init");
+ riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
+ generic_info->version_specific = calloc(1, sizeof(riscv013_info_t));
+ if (!generic_info->version_specific)
+ return ERROR_FAIL;
+ riscv013_info_t *info = get_info(target);
+
+ target->reg_cache = calloc(1, sizeof(*target->reg_cache));
+ target->reg_cache->name = "RISC-V registers";
+ target->reg_cache->num_regs = REG_COUNT;
+
+ target->reg_cache->reg_list = calloc(REG_COUNT, sizeof(struct reg));
+
+ const unsigned int max_reg_name_len = 12;
+ info->reg_names = calloc(1, REG_COUNT * max_reg_name_len);
+ char *reg_name = info->reg_names;
+ info->reg_values = NULL;
+
+ for (unsigned int i = 0; i < REG_COUNT; i++) {
+ struct reg *r = &target->reg_cache->reg_list[i];
+ r->number = i;
+ r->caller_save = true;
+ r->dirty = false;
+ r->valid = false;
+ r->exist = true;
+ r->type = &riscv_reg_arch_type;
+ r->arch_info = target;
+ if (i <= REG_XPR31) {
+ sprintf(reg_name, "x%d", i);
+ } else if (i == REG_PC) {
+ sprintf(reg_name, "pc");
+ } else if (i >= REG_FPR0 && i <= REG_FPR31) {
+ sprintf(reg_name, "f%d", i - REG_FPR0);
+ } else if (i >= REG_CSR0 && i <= REG_CSR4095) {
+ sprintf(reg_name, "csr%d", i - REG_CSR0);
+ } else if (i == REG_PRIV) {
+ sprintf(reg_name, "priv");
+ }
+ if (reg_name[0]) {
+ r->name = reg_name;
+ }
+ reg_name += strlen(reg_name) + 1;
+ assert(reg_name < info->reg_names + REG_COUNT * max_reg_name_len);
+ }
+ update_reg_list(target);
+
+ memset(info->trigger_unique_id, 0xff, sizeof(info->trigger_unique_id));
+
+ return ERROR_OK;
+}
+
+static void deinit_target(struct target *target)
+{
+ LOG_DEBUG("riscv_deinit_target()");
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ free(info->version_specific);
+ info->version_specific = NULL;
+}
+
+static int add_trigger(struct target *target, struct trigger *trigger)
+{
+ riscv013_info_t *info = get_info(target);
+
+ maybe_read_tselect(target);
+
+ unsigned int i;
+ for (i = 0; i < info->trigger_count; i++) {
+ if (info->trigger_unique_id[i] != -1) {
+ continue;
+ }
+
+ write_csr(target, CSR_TSELECT, i);
+
+ uint64_t tdata1;
+ read_csr(target, &tdata1, CSR_TDATA1);
+ int type = get_field(tdata1, MCONTROL_TYPE(xlen(target)));
+
+ if (type != 2) {
+ continue;
+ }
+
+ if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
+ // Trigger is already in use, presumably by user code.
+ continue;
+ }
+
+ // address/data match trigger
+ tdata1 |= MCONTROL_DMODE(xlen(target));
+ tdata1 = set_field(tdata1, MCONTROL_ACTION,
+ MCONTROL_ACTION_DEBUG_MODE);
+ tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
+ tdata1 |= MCONTROL_M;
+ if (info->misa & (1 << ('H' - 'A')))
+ tdata1 |= MCONTROL_H;
+ if (info->misa & (1 << ('S' - 'A')))
+ tdata1 |= MCONTROL_S;
+ if (info->misa & (1 << ('U' - 'A')))
+ tdata1 |= MCONTROL_U;
+
+ if (trigger->execute)
+ tdata1 |= MCONTROL_EXECUTE;
+ if (trigger->read)
+ tdata1 |= MCONTROL_LOAD;
+ if (trigger->write)
+ tdata1 |= MCONTROL_STORE;
+
+ write_csr(target, CSR_TDATA1, tdata1);
+
+ uint64_t tdata1_rb;
+ read_csr(target, &tdata1_rb, CSR_TDATA1);
+ LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
+
+ if (tdata1 != tdata1_rb) {
+ LOG_DEBUG("Trigger %d doesn't support what we need; After writing 0x%"
+ PRIx64 " to tdata1 it contains 0x%" PRIx64,
+ i, tdata1, tdata1_rb);
+ write_csr(target, CSR_TDATA1, 0);
+ continue;
+ }
+
+ write_csr(target, CSR_TDATA2, trigger->address);
+
+ LOG_DEBUG("Using resource %d for bp %d", i,
+ trigger->unique_id);
+ info->trigger_unique_id[i] = trigger->unique_id;
+ break;
+ }
+ if (i >= info->trigger_count) {
+ LOG_ERROR("Couldn't find an available hardware trigger.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ return ERROR_OK;
+}
+
+static int remove_trigger(struct target *target, struct trigger *trigger)
+{
+ riscv013_info_t *info = get_info(target);
+
+ maybe_read_tselect(target);
+
+ unsigned int i;
+ for (i = 0; i < info->trigger_count; i++) {
+ if (info->trigger_unique_id[i] == trigger->unique_id) {
+ break;
+ }
+ }
+ if (i >= info->trigger_count) {
+ LOG_ERROR("Couldn't find the hardware resources used by hardware "
+ "trigger.");
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
+ write_csr(target, CSR_TSELECT, i);
+ write_csr(target, CSR_TDATA1, 0);
+ info->trigger_unique_id[i] = -1;
+
+ return ERROR_OK;
+}
+
+static void trigger_from_breakpoint(struct trigger *trigger,
+ const struct breakpoint *breakpoint)
+{
+ trigger->address = breakpoint->address;
+ trigger->length = breakpoint->length;
+ trigger->mask = ~0LL;
+ trigger->read = false;
+ trigger->write = false;
+ trigger->execute = true;
+ // unique_id is unique across both breakpoints and watchpoints.
+ trigger->unique_id = breakpoint->unique_id;
+}
+
+static void trigger_from_watchpoint(struct trigger *trigger,
+ const struct watchpoint *watchpoint)
+{
+ trigger->address = watchpoint->address;
+ trigger->length = watchpoint->length;
+ trigger->mask = watchpoint->mask;
+ trigger->value = watchpoint->value;
+ trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
+ trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
+ trigger->execute = false;
+ // unique_id is unique across both breakpoints and watchpoints.
+ trigger->unique_id = watchpoint->unique_id;
+}
+
+static int add_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ if (breakpoint->type == BKPT_SOFT) {
+ if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
+ breakpoint->orig_instr) != ERROR_OK) {
+ LOG_ERROR("Failed to read original instruction at 0x%x",
+ breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ int retval;
+ if (breakpoint->length == 4) {
+ retval = target_write_u32(target, breakpoint->address, ebreak());
+ } else {
+ retval = target_write_u16(target, breakpoint->address, ebreak_c());
+ }
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%x",
+ breakpoint->length, breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ } else if (breakpoint->type == BKPT_HARD) {
+ struct trigger trigger;
+ trigger_from_breakpoint(&trigger, breakpoint);
+ int result = add_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ } else {
+ LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ breakpoint->set = true;
+
+ return ERROR_OK;
+}
+
+static int remove_breakpoint(struct target *target,
+ struct breakpoint *breakpoint)
+{
+ if (breakpoint->type == BKPT_SOFT) {
+ if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
+ breakpoint->orig_instr) != ERROR_OK) {
+ LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
+ "0x%x", breakpoint->length, breakpoint->address);
+ return ERROR_FAIL;
+ }
+
+ } else if (breakpoint->type == BKPT_HARD) {
+ struct trigger trigger;
+ trigger_from_breakpoint(&trigger, breakpoint);
+ int result = remove_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ } else {
+ LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ breakpoint->set = false;
+
+ return ERROR_OK;
+}
+
+static int add_watchpoint(struct target *target,
+ struct watchpoint *watchpoint)
+{
+ struct trigger trigger;
+ trigger_from_watchpoint(&trigger, watchpoint);
+
+ int result = add_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ watchpoint->set = true;
+
+ return ERROR_OK;
+}
+
+static int remove_watchpoint(struct target *target,
+ struct watchpoint *watchpoint)
+{
+ struct trigger trigger;
+ trigger_from_watchpoint(&trigger, watchpoint);
+
+ int result = remove_trigger(target, &trigger);
+ if (result != ERROR_OK) {
+ return result;
+ }
+ watchpoint->set = false;
+
+ return ERROR_OK;
+}
+
+static int strict_step(struct target *target, bool announce)
+{
+ riscv013_info_t *info = get_info(target);
+
+ LOG_DEBUG("enter");
+
+ struct breakpoint *breakpoint = target->breakpoints;
+ while (breakpoint) {
+ remove_breakpoint(target, breakpoint);
+ breakpoint = breakpoint->next;
+ }
+
+ struct watchpoint *watchpoint = target->watchpoints;
+ while (watchpoint) {
+ remove_watchpoint(target, watchpoint);
+ watchpoint = watchpoint->next;
+ }
+
+ int result = full_step(target, announce);
+ if (result != ERROR_OK)
+ return result;
+
+ breakpoint = target->breakpoints;
+ while (breakpoint) {
+ add_breakpoint(target, breakpoint);
+ breakpoint = breakpoint->next;
+ }
+
+ watchpoint = target->watchpoints;
+ while (watchpoint) {
+ add_watchpoint(target, watchpoint);
+ watchpoint = watchpoint->next;
+ }
+
+ info->need_strict_step = false;
+
+ return ERROR_OK;
+}
+
+static int step(struct target *target, int current, uint32_t address,
+ int handle_breakpoints)
+{
+ riscv013_info_t *info = get_info(target);
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ if (!current) {
+ if (xlen(target) > 32) {
+ LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
+ xlen(target));
+ }
+ int result = register_write(target, REG_PC, address);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ if (info->need_strict_step || handle_breakpoints) {
+ int result = strict_step(target, true);
+ if (result != ERROR_OK)
+ return result;
+ } else {
+ return resume(target, 0, true);
+ }
+
+ return ERROR_OK;
+}
+
+static int examine(struct target *target)
+{
+ // Don't need to select dbus, since the first thing we do is read dtmcontrol.
+
+ uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
+ LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
+ LOG_DEBUG(" dbusreset=%d", get_field(dtmcontrol, DTM_DTMCONTROL_DBUSRESET));
+ LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTM_DTMCONTROL_IDLE));
+ LOG_DEBUG(" dbusstat=%d", get_field(dtmcontrol, DTM_DTMCONTROL_DBUSSTAT));
+ LOG_DEBUG(" abits=%d", get_field(dtmcontrol, DTM_DTMCONTROL_ABITS));
+ LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTM_DTMCONTROL_VERSION));
+ if (dtmcontrol == 0) {
+ LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
+ return ERROR_FAIL;
+ }
+ if (get_field(dtmcontrol, DTM_DTMCONTROL_VERSION) != 1) {
+ LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
+ get_field(dtmcontrol, DTM_DTMCONTROL_VERSION), dtmcontrol);
+ return ERROR_FAIL;
+ }
+
+ riscv013_info_t *info = get_info(target);
+ info->abits = get_field(dtmcontrol, DTM_DTMCONTROL_ABITS);
+ info->dtmcontrol_idle = get_field(dtmcontrol, DTM_DTMCONTROL_IDLE);
+ if (info->dtmcontrol_idle == 0) {
+ // Some old SiFive cores don't set idle but need it to be 1.
+ uint32_t idcode = idcode_scan(target);
+ if (idcode == 0x10e31913)
+ info->dtmcontrol_idle = 1;
+ }
+
+ uint32_t dmcontrol = dbus_read(target, DMI_DMCONTROL);
+ LOG_DEBUG("dmcontrol: 0x%08x", dmcontrol);
+ LOG_DEBUG(" halt=%d", get_field(dmcontrol, DMI_DMCONTROL_HALT));
+ LOG_DEBUG(" reset=%d", get_field(dmcontrol, DMI_DMCONTROL_RESET));
+ LOG_DEBUG(" dmactive=%d", get_field(dmcontrol, DMI_DMCONTROL_DMACTIVE));
+ LOG_DEBUG(" hartid=0x%x", get_field(dmcontrol, DMI_DMCONTROL_HARTID));
+ LOG_DEBUG(" authenticated=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHENTICATED));
+ LOG_DEBUG(" authbusy=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHBUSY));
+ LOG_DEBUG(" authtype=%d", get_field(dmcontrol, DMI_DMCONTROL_AUTHTYPE));
+ LOG_DEBUG(" version=%d", get_field(dmcontrol, DMI_DMCONTROL_VERSION));
+
+ if (get_field(dmcontrol, DMI_DMCONTROL_VERSION) != 1) {
+ LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
+ "(dmcontrol=0x%x)", get_field(dmcontrol, DMI_DMCONTROL_VERSION), dmcontrol);
+ return ERROR_FAIL;
+ }
+
+ if (!get_field(dmcontrol, DMI_DMCONTROL_AUTHENTICATED)) {
+ LOG_ERROR("Authentication required by RISC-V core but not "
+ "supported by OpenOCD. dmcontrol=0x%x", dmcontrol);
+ return ERROR_FAIL;
+ }
+
+ // Check that abstract data registers are accessible.
+ uint32_t abstractcs = dbus_read(target, DMI_ABSTRACTCS);
+ info->datacount = get_field(abstractcs, DMI_ABSTRACTCS_DATACOUNT);
+ LOG_DEBUG("abstractcs=0x%x", abstractcs);
+ LOG_DEBUG(" datacount=%d", info->datacount);
+
+ uint32_t accesscs = dbus_read(target, DMI_ACCESSCS);
+ info->progsize = get_field(abstractcs, DMI_ACCESSCS_PROGSIZE);
+ LOG_DEBUG("accesscs=0x%x", accesscs);
+ LOG_DEBUG(" progsize=%d", info->progsize);
+
+ uint32_t value = 0x53467665;
+ for (unsigned i = 0; i < info->datacount; i++) {
+ dbus_write(target, DMI_DATA0 + i, value);
+ value += 0x52534335;
+ }
+
+ for (unsigned i = 0; i < info->progsize; i++) {
+ dbus_write(target, DMI_IBUF0 + i, value);
+ value += 0x52534335;
+ }
+
+ value = 0x53467665;
+ for (unsigned i = 0; i < info->datacount; i++) {
+ uint32_t check = dbus_read(target, DMI_DATA0 + i);
+ if (check != value) {
+ LOG_ERROR("Wrote 0x%x to dbus address 0x%x but got back 0x%x",
+ value, DMI_DATA0 + i, check);
+ return ERROR_FAIL;
+ }
+ value += 0x52534335;
+ }
+ for (unsigned i = 0; i < info->progsize; i++) {
+ uint32_t check = dbus_read(target, DMI_IBUF0 + i);
+ if (check != value) {
+ LOG_ERROR("Wrote 0x%x to dbus address 0x%x but got back 0x%x",
+ value, DMI_IBUF0 + i, check);
+ return ERROR_FAIL;
+ }
+ value += 0x52534335;
+ }
+
+ // Figure out XLEN, and test writing all of Debug RAM while we're at it.
+ cache_set32(target, 0, xori(S1, ZERO, -1));
+ // 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
+ cache_set32(target, 1, srli(S1, S1, 31));
+ // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
+ cache_set32(target, 3, srli(S1, S1, 31));
+ // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
+ cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
+ cache_set_jump(target, 5);
+ for (unsigned i = 6; i < info->dramsize; i++) {
+ cache_set32(target, i, i * 0x01020304);
+ }
+
+ cache_write(target, 0, false);
+
+ // Check that we can actually read/write dram.
+ if (cache_check(target) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ cache_write(target, 0, true);
+ cache_invalidate(target);
+
+ uint32_t word0 = cache_get32(target, 0);
+ uint32_t word1 = cache_get32(target, 1);
+ riscv_info_t *generic_info = (riscv_info_t *) target->arch_info;
+ if (word0 == 1 && word1 == 0) {
+ generic_info->xlen = 32;
+ } else if (word0 == 0xffffffff && word1 == 3) {
+ generic_info->xlen = 64;
+ } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
+ generic_info->xlen = 128;
+ } else {
+ uint32_t exception = cache_get32(target, info->dramsize-1);
+ LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
+ word0, word1, exception);
+ dump_debug_ram(target);
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("Discovered XLEN is %d", xlen(target));
+
+ // Update register list to match discovered XLEN.
+ update_reg_list(target);
+
+ if (read_csr(target, &info->misa, CSR_MISA) != ERROR_OK) {
+ LOG_ERROR("Failed to read misa.");
+ return ERROR_FAIL;
+ }
+
+ info->never_halted = true;
+
+ int result = riscv013_poll(target);
+ if (result != ERROR_OK) {
+ return result;
+ }
+
+ target_set_examined(target);
+ LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64, xlen(target), info->misa);
+
+ return ERROR_OK;
+}
+
+static riscv_error_t handle_halt_routine(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+
+ scans_t *scans = scans_new(target, 256);
+
+ // Read all GPRs as fast as we can, because gdb is going to ask for them
+ // anyway. Reading them one at a time is much slower.
+
+ // Write the jump back to address 1.
+ scans_add_write_jump(scans, 1, false);
+ for (int reg = 1; reg < 32; reg++) {
+ if (reg == S0 || reg == S1) {
+ continue;
+ }
+
+ // Write store instruction.
+ scans_add_write_store(scans, 0, reg, SLOT0, true);
+
+ // Read value.
+ scans_add_read(scans, SLOT0, false);
+ }
+
+ // Write store of s0 at index 1.
+ scans_add_write_store(scans, 1, S0, SLOT0, false);
+ // Write jump at index 2.
+ scans_add_write_jump(scans, 2, false);
+
+ // Read S1 from debug RAM
+ scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
+ // Read value.
+ scans_add_read(scans, SLOT0, false);
+
+ // Read S0 from dscratch
+ unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
+ for (unsigned int i = 0; i < DIM(csr); i++) {
+ scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
+ scans_add_read(scans, SLOT0, false);
+ }
+
+ // Final read to get the last value out.
+ scans_add_read32(scans, 4, false);
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ unsigned int dbus_busy = 0;
+ unsigned int interrupt_set = 0;
+ unsigned result = 0;
+ uint64_t value = 0;
+ reg_cache_set(target, 0, 0);
+ // The first scan result is the result from something old we don't care
+ // about.
+ for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
+ dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
+ uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
+ info->abits);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug access failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ if (data & DMCONTROL_INTERRUPT) {
+ interrupt_set++;
+ break;
+ }
+ if (address == 4 || address == 5) {
+ unsigned int reg;
+ switch (result) {
+ case 0: reg = 1; break;
+ case 1: reg = 2; break;
+ case 2: reg = 3; break;
+ case 3: reg = 4; break;
+ case 4: reg = 5; break;
+ case 5: reg = 6; break;
+ case 6: reg = 7; break;
+ // S0
+ // S1
+ case 7: reg = 10; break;
+ case 8: reg = 11; break;
+ case 9: reg = 12; break;
+ case 10: reg = 13; break;
+ case 11: reg = 14; break;
+ case 12: reg = 15; break;
+ case 13: reg = 16; break;
+ case 14: reg = 17; break;
+ case 15: reg = 18; break;
+ case 16: reg = 19; break;
+ case 17: reg = 20; break;
+ case 18: reg = 21; break;
+ case 19: reg = 22; break;
+ case 20: reg = 23; break;
+ case 21: reg = 24; break;
+ case 22: reg = 25; break;
+ case 23: reg = 26; break;
+ case 24: reg = 27; break;
+ case 25: reg = 28; break;
+ case 26: reg = 29; break;
+ case 27: reg = 30; break;
+ case 28: reg = 31; break;
+ case 29: reg = S1; break;
+ case 30: reg = S0; break;
+ case 31: reg = CSR_DPC; break;
+ case 32: reg = CSR_DCSR; break;
+ default:
+ assert(0);
+ }
+ if (xlen(target) == 32) {
+ reg_cache_set(target, reg, data & 0xffffffff);
+ result++;
+ } else if (xlen(target) == 64) {
+ if (address == 4) {
+ value = data & 0xffffffff;
+ } else if (address == 5) {
+ reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
+ value = 0;
+ result++;
+ }
+ }
+ }
+ }
+
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ return RE_AGAIN;
+ }
+ if (interrupt_set) {
+ increase_interrupt_high_delay(target);
+ return RE_AGAIN;
+ }
+
+ // TODO: get rid of those 2 variables and talk to the cache directly.
+ info->dpc = reg_cache_get(target, CSR_DPC);
+ info->dcsr = reg_cache_get(target, CSR_DCSR);
+
+ scans = scans_delete(scans);
+
+ cache_invalidate(target);
+
+ return RE_OK;
+
+error:
+ scans = scans_delete(scans);
+ return RE_FAIL;
+}
+
+static int handle_halt(struct target *target, bool announce)
+{
+ riscv013_info_t *info = get_info(target);
+ target->state = TARGET_HALTED;
+
+ riscv_error_t re;
+ do {
+ re = handle_halt_routine(target);
+ } while (re == RE_AGAIN);
+ if (re != RE_OK) {
+ LOG_ERROR("handle_halt_routine failed");
+ return ERROR_FAIL;
+ }
+
+ int cause = get_field(info->dcsr, DCSR_CAUSE);
+ switch (cause) {
+ case DCSR_CAUSE_SWBP:
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ break;
+ case DCSR_CAUSE_HWBP:
+ target->debug_reason = DBG_REASON_WPTANDBKPT;
+ // If we halted because of a data trigger, gdb doesn't know to do
+ // the disable-breakpoints-step-enable-breakpoints dance.
+ info->need_strict_step = true;
+ break;
+ case DCSR_CAUSE_DEBUGINT:
+ target->debug_reason = DBG_REASON_DBGRQ;
+ break;
+ case DCSR_CAUSE_STEP:
+ target->debug_reason = DBG_REASON_SINGLESTEP;
+ break;
+ case DCSR_CAUSE_HALT:
+ default:
+ LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
+ cause, info->dcsr);
+ }
+
+ if (info->never_halted) {
+ info->never_halted = false;
+
+ // Disable any hardware triggers that have dmode set. We can't have set
+ // them ourselves. Maybe they're left over from some killed debug
+ // session.
+ // Count the number of triggers while we're at it.
+
+ int result = maybe_read_tselect(target);
+ if (result != ERROR_OK)
+ return result;
+ for (info->trigger_count = 0; info->trigger_count < MAX_HWBPS; info->trigger_count++) {
+ write_csr(target, CSR_TSELECT, info->trigger_count);
+ uint64_t tselect_rb;
+ read_csr(target, &tselect_rb, CSR_TSELECT);
+ if (info->trigger_count != tselect_rb)
+ break;
+ uint64_t tdata1;
+ read_csr(target, &tdata1, CSR_TDATA1);
+ if ((tdata1 & MCONTROL_DMODE(xlen(target))) &&
+ (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD))) {
+ write_csr(target, CSR_TDATA1, 0);
+ }
+ }
+ }
+
+ if (announce) {
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+ }
+
+ const char *cause_string[] = {
+ "none",
+ "software breakpoint",
+ "hardware trigger",
+ "debug interrupt",
+ "step",
+ "halt"
+ };
+ // This is logged to the user so that gdb will show it when a user types
+ // 'monitor reset init'. At that time gdb appears to have the pc cached
+ // still so if a user manually inspects the pc it will still have the old
+ // value.
+ LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
+
+ return ERROR_OK;
+}
+
+static int poll_target(struct target *target, bool announce)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // Inhibit debug logging during poll(), which isn't usually interesting and
+ // just fills up the screen/logs with clutter.
+ int old_debug_level = debug_level;
+ if (debug_level >= LOG_LVL_DEBUG) {
+ debug_level = LOG_LVL_INFO;
+ }
+ bits_t bits = read_bits(target);
+ debug_level = old_debug_level;
+
+ if (bits.haltnot && bits.interrupt) {
+ target->state = TARGET_DEBUG_RUNNING;
+ LOG_DEBUG("debug running");
+ } else if (bits.haltnot && !bits.interrupt) {
+ if (target->state != TARGET_HALTED) {
+ return handle_halt(target, announce);
+ }
+ } else if (!bits.haltnot && bits.interrupt) {
+ // Target is halting. There is no state for that, so don't change anything.
+ LOG_DEBUG("halting");
+ } else if (!bits.haltnot && !bits.interrupt) {
+ target->state = TARGET_RUNNING;
+ }
+
+ return ERROR_OK;
+}
+
+static int riscv013_poll(struct target *target)
+{
+ return poll_target(target, true);
+}
+
+static int riscv013_resume(struct target *target, int current, uint32_t address,
+ int handle_breakpoints, int debug_execution)
+{
+ riscv013_info_t *info = get_info(target);
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ if (!current) {
+ if (xlen(target) > 32) {
+ LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
+ xlen(target));
+ }
+ int result = register_write(target, REG_PC, address);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ if (info->need_strict_step || handle_breakpoints) {
+ int result = strict_step(target, false);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ return resume(target, debug_execution, false);
+}
+
+static int assert_reset(struct target *target)
+{
+ riscv013_info_t *info = get_info(target);
+ // TODO: Maybe what I implemented here is more like soft_reset_halt()?
+
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // The only assumption we can make is that the TAP was reset.
+ if (wait_for_debugint_clear(target, true) != ERROR_OK) {
+ LOG_ERROR("Debug interrupt didn't clear.");
+ return ERROR_FAIL;
+ }
+
+ // Not sure what we should do when there are multiple cores.
+ // Here just reset the single hart we're talking to.
+ info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
+ DCSR_EBREAKU | DCSR_HALT;
+ if (target->reset_halt) {
+ info->dcsr |= DCSR_NDRESET;
+ } else {
+ info->dcsr |= DCSR_FULLRESET;
+ }
+ dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
+ dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
+ // We shouldn't actually need the jump because a reset should happen.
+ dram_write_jump(target, 2, false);
+ dram_write32(target, 4, info->dcsr, true);
+ cache_invalidate(target);
+
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+}
+
+static int deassert_reset(struct target *target)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+ if (target->reset_halt) {
+ return wait_for_state(target, TARGET_HALTED);
+ } else {
+ return wait_for_state(target, TARGET_RUNNING);
+ }
+}
+
+static int read_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+ switch (size) {
+ case 1:
+ cache_set32(target, 1, lb(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 2:
+ cache_set32(target, 1, lh(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ case 4:
+ cache_set32(target, 1, lw(S1, S0, 0));
+ cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
+ }
+ cache_set_jump(target, 3);
+ cache_write(target, CACHE_NO_READ, false);
+
+ riscv013_info_t *info = get_info(target);
+ const int max_batch_size = 256;
+ scans_t *scans = scans_new(target, max_batch_size);
+
+ uint32_t result_value = 0x777;
+ uint32_t i = 0;
+ while (i < count + 3) {
+ unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
+ scans_reset(scans);
+
+ for (unsigned int j = 0; j < batch_size; j++) {
+ if (i + j == count) {
+ // Just insert a read so we can scan out the last value.
+ scans_add_read32(scans, 4, false);
+ } else if (i + j >= count + 1) {
+ // And check for errors.
+ scans_add_read32(scans, info->dramsize-1, false);
+ } else {
+ // Write the next address and set interrupt.
+ uint32_t offset = size * (i + j);
+ scans_add_write32(scans, 4, address + offset, true);
+ }
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ int dbus_busy = 0;
+ int execute_busy = 0;
+ for (unsigned int j = 0; j < batch_size; j++) {
+ dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
+ DBUS_DATA_SIZE);
+ if (data & DMCONTROL_INTERRUPT) {
+ execute_busy++;
+ }
+ if (i + j == count + 2) {
+ result_value = data;
+ } else if (i + j > 1) {
+ uint32_t offset = size * (i + j - 2);
+ switch (size) {
+ case 1:
+ buffer[offset] = data;
+ break;
+ case 2:
+ buffer[offset] = data;
+ buffer[offset+1] = data >> 8;
+ break;
+ case 4:
+ buffer[offset] = data;
+ buffer[offset+1] = data >> 8;
+ buffer[offset+2] = data >> 16;
+ buffer[offset+3] = data >> 24;
+ break;
+ }
+ }
+ LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
+ }
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ }
+ if (execute_busy) {
+ increase_interrupt_high_delay(target);
+ }
+ if (dbus_busy || execute_busy) {
+ wait_for_debugint_clear(target, false);
+
+ // Retry.
+ LOG_INFO("Retrying memory read starting from 0x%x with more delays",
+ address + size * i);
+ } else {
+ i += batch_size;
+ }
+ }
+
+ if (result_value != 0) {
+ LOG_USER("Core got an exception (0x%x) while reading from 0x%x",
+ result_value, address + size * (count-1));
+ if (count > 1) {
+ LOG_USER("(It may have failed between 0x%x and 0x%x as well, but we "
+ "didn't check then.)",
+ address, address + size * (count-2) + size - 1);
+ }
+ goto error;
+ }
+
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_OK;
+
+error:
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_FAIL;
+}
+
+static int setup_write_memory(struct target *target, uint32_t size)
+{
+ switch (size) {
+ case 1:
+ cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sb(S0, T0, 0));
+ break;
+ case 2:
+ cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sh(S0, T0, 0));
+ break;
+ case 4:
+ cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+ cache_set32(target, 1, sw(S0, T0, 0));
+ break;
+ default:
+ LOG_ERROR("Unsupported size: %d", size);
+ return ERROR_FAIL;
+ }
+ cache_set32(target, 2, addi(T0, T0, size));
+ cache_set_jump(target, 3);
+ cache_write(target, 4, false);
+
+ return ERROR_OK;
+}
+
+static int write_memory(struct target *target, uint32_t address,
+ uint32_t size, uint32_t count, const uint8_t *buffer)
+{
+ riscv013_info_t *info = get_info(target);
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
+ // Set up the address.
+ cache_set_store(target, 0, T0, SLOT1);
+ cache_set_load(target, 1, T0, SLOT0);
+ cache_set_jump(target, 2);
+ cache_set(target, SLOT0, address);
+ if (cache_write(target, 5, true) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ uint64_t t0 = cache_get(target, SLOT1);
+ LOG_DEBUG("t0 is 0x%" PRIx64, t0);
+
+ if (setup_write_memory(target, size) != ERROR_OK) {
+ return ERROR_FAIL;
+ }
+
+ const int max_batch_size = 256;
+ scans_t *scans = scans_new(target, max_batch_size);
+
+ uint32_t result_value = 0x777;
+ uint32_t i = 0;
+ while (i < count + 2) {
+ unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
+ scans_reset(scans);
+
+ for (unsigned int j = 0; j < batch_size; j++) {
+ if (i + j >= count) {
+ // Check for an exception.
+ scans_add_read32(scans, info->dramsize-1, false);
+ } else {
+ // Write the next value and set interrupt.
+ uint32_t value;
+ uint32_t offset = size * (i + j);
+ switch (size) {
+ case 1:
+ value = buffer[offset];
+ break;
+ case 2:
+ value = buffer[offset] |
+ (buffer[offset+1] << 8);
+ break;
+ case 4:
+ value = buffer[offset] |
+ ((uint32_t) buffer[offset+1] << 8) |
+ ((uint32_t) buffer[offset+2] << 16) |
+ ((uint32_t) buffer[offset+3] << 24);
+ break;
+ default:
+ goto error;
+ }
+
+ scans_add_write32(scans, 4, value, true);
+ }
+ }
+
+ int retval = scans_execute(scans);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("JTAG execute failed: %d", retval);
+ goto error;
+ }
+
+ int dbus_busy = 0;
+ int execute_busy = 0;
+ for (unsigned int j = 0; j < batch_size; j++) {
+ dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
+ DBUS_OP_SIZE);
+ switch (status) {
+ case DBUS_STATUS_SUCCESS:
+ break;
+ case DBUS_STATUS_FAILED:
+ LOG_ERROR("Debug RAM write failed. Hardware error?");
+ goto error;
+ case DBUS_STATUS_BUSY:
+ dbus_busy++;
+ break;
+ default:
+ LOG_ERROR("Got invalid bus access status: %d", status);
+ return ERROR_FAIL;
+ }
+ int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
+ if (interrupt) {
+ execute_busy++;
+ }
+ if (i + j == count + 1) {
+ result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
+ }
+ }
+ if (dbus_busy) {
+ increase_dbus_busy_delay(target);
+ }
+ if (execute_busy) {
+ increase_interrupt_high_delay(target);
+ }
+ if (dbus_busy || execute_busy) {
+ wait_for_debugint_clear(target, false);
+
+ // Retry.
+ // Set t0 back to what it should have been at the beginning of this
+ // batch.
+ LOG_INFO("Retrying memory write starting from 0x%x with more delays",
+ address + size * i);
+
+ cache_clean(target);
+
+ if (write_gpr(target, T0, address + size * i) != ERROR_OK) {
+ goto error;
+ }
+
+ if (setup_write_memory(target, size) != ERROR_OK) {
+ goto error;
+ }
+ } else {
+ i += batch_size;
+ }
+ }
+
+ if (result_value != 0) {
+ LOG_ERROR("Core got an exception (0x%x) while writing to 0x%x",
+ result_value, address + size * (count-1));
+ if (count > 1) {
+ LOG_ERROR("(It may have failed between 0x%x and 0x%x as well, but we "
+ "didn't check then.)",
+ address, address + size * (count-2) + size - 1);
+ }
+ goto error;
+ }
+
+ cache_clean(target);
+ return register_write(target, T0, t0);
+
+error:
+ scans_delete(scans);
+ cache_clean(target);
+ return ERROR_FAIL;
+}
+
+static int arch_state(struct target *target)
+{
+ return ERROR_OK;
+}
+
+struct target_type riscv013_target =
+{
+ .name = "riscv",
+
+ .init_target = init_target,
+ .deinit_target = deinit_target,
+ .examine = examine,
+
+ /* poll current target status */
+ .poll = riscv013_poll,
+
+ .halt = halt,
+ .resume = riscv013_resume,
+ .step = step,
+
+ .assert_reset = assert_reset,
+ .deassert_reset = deassert_reset,
+
+ .read_memory = read_memory,
+ .write_memory = write_memory,
+
+ .add_breakpoint = add_breakpoint,
+ .remove_breakpoint = remove_breakpoint,
+
+ .add_watchpoint = add_watchpoint,
+ .remove_watchpoint = remove_watchpoint,
+
+ .arch_state = arch_state,
+};
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index fb48ca6..3118e52 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -11,10 +11,10 @@
#include "target_type.h"
#include "log.h"
#include "jtag/jtag.h"
-#include "opcodes.h"
#include "register.h"
#include "breakpoints.h"
#include "helper/time_support.h"
+#include "riscv.h"
/**
* Since almost everything can be accomplish by scanning the dbus register, all
@@ -168,6 +168,22 @@ enum {
#define MAX_HWBPS 16
#define DRAM_CACHE_SIZE 16
+uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
+struct scan_field select_dtmcontrol = {
+ .in_value = NULL,
+ .out_value = ir_dtmcontrol
+};
+uint8_t ir_dbus[1] = {DBUS};
+struct scan_field select_dbus = {
+ .in_value = NULL,
+ .out_value = ir_dbus
+};
+uint8_t ir_idcode[1] = {0x1};
+struct scan_field select_idcode = {
+ .in_value = NULL,
+ .out_value = ir_idcode
+};
+
struct trigger {
uint64_t address;
uint32_t length;
@@ -177,162 +193,6 @@ struct trigger {
int unique_id;
};
-struct memory_cache_line {
- uint32_t data;
- bool valid;
- bool dirty;
-};
-
-typedef struct {
- /* Number of address bits in the dbus register. */
- uint8_t addrbits;
- /* Width of a GPR (and many other things) in bits. */
- uint8_t xlen;
- /* Number of words in Debug RAM. */
- unsigned int dramsize;
- uint64_t dcsr;
- uint64_t dpc;
- uint64_t misa;
- uint64_t tselect;
- bool tselect_dirty;
- /* The value that mstatus actually has on the target right now. This is not
- * the value we present to the user. That one may be stored in the
- * reg_cache. */
- uint64_t mstatus_actual;
-
- struct memory_cache_line dram_cache[DRAM_CACHE_SIZE];
-
- /* Single buffer that contains all register names, instead of calling
- * malloc for each register. Needs to be freed when reg_list is freed. */
- char *reg_names;
- /* Single buffer that contains all register values. */
- void *reg_values;
-
- // For each physical trigger, contains -1 if the hwbp is available, or the
- // unique_id of the breakpoint/watchpoint that is using it.
- int trigger_unique_id[MAX_HWBPS];
-
- unsigned int trigger_count;
-
- // Number of run-test/idle cycles the target requests we do after each dbus
- // access.
- unsigned int dtmcontrol_idle;
-
- // This value is incremented every time a dbus access comes back as "busy".
- // It's used to determine how many run-test/idle cycles to feed the target
- // in between accesses.
- unsigned int dbus_busy_delay;
-
- // This value is incremented every time we read the debug interrupt as
- // high. It's used to add extra run-test/idle cycles after setting debug
- // interrupt high, so ideally we never have to perform a whole extra scan
- // before the interrupt is cleared.
- unsigned int interrupt_high_delay;
-
- bool need_strict_step;
- bool never_halted;
-} riscv_info_t;
-
-typedef struct {
- bool haltnot;
- bool interrupt;
-} bits_t;
-
-/*** Necessary prototypes. ***/
-
-static int riscv_poll(struct target *target);
-static int poll_target(struct target *target, bool announce);
-static int register_get(struct reg *reg);
-
-/*** Utility functions. ***/
-
-static uint8_t ir_dtmcontrol[1] = {DTMCONTROL};
-static struct scan_field select_dtmcontrol = {
- .in_value = NULL,
- .out_value = ir_dtmcontrol
-};
-static uint8_t ir_dbus[1] = {DBUS};
-static struct scan_field select_dbus = {
- .in_value = NULL,
- .out_value = ir_dbus
-};
-static uint8_t ir_idcode[1] = {0x1};
-static struct scan_field select_idcode = {
- .in_value = NULL,
- .out_value = ir_idcode
-};
-#define DEBUG_LENGTH 264
-
-static uint32_t load(const struct target *target, unsigned int rd,
- unsigned int base, uint16_t offset)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- switch (info->xlen) {
- case 32:
- return lw(rd, base, offset);
- case 64:
- return ld(rd, base, offset);
- }
- assert(0);
-}
-
-static uint32_t store(const struct target *target, unsigned int src,
- unsigned int base, uint16_t offset)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- switch (info->xlen) {
- case 32:
- return sw(src, base, offset);
- case 64:
- return sd(src, base, offset);
- }
- assert(0);
-}
-
-static unsigned int slot_offset(const struct target *target, slot_t slot)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- switch (info->xlen) {
- case 32:
- switch (slot) {
- case SLOT0: return 4;
- case SLOT1: return 5;
- case SLOT_LAST: return info->dramsize-1;
- }
- case 64:
- switch (slot) {
- case SLOT0: return 4;
- case SLOT1: return 6;
- case SLOT_LAST: return info->dramsize-2;
- }
- }
- LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
- info->xlen, slot);
- assert(0);
-}
-
-static uint32_t load_slot(const struct target *target, unsigned int dest,
- slot_t slot)
-{
- unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
- return load(target, dest, ZERO, offset);
-}
-
-static uint32_t store_slot(const struct target *target, unsigned int src,
- slot_t slot)
-{
- unsigned int offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
- return store(target, src, ZERO, offset);
-}
-
-static uint16_t dram_address(unsigned int index)
-{
- if (index < 0x10)
- return index;
- else
- return 0x40 + index - 0x10;
-}
-
static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
{
struct scan_field field;
@@ -348,15 +208,15 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
field.in_value = in_value;
jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
+ /* Always return to dbus. */
+ jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
+
int retval = jtag_execute_queue();
if (retval != ERROR_OK) {
LOG_ERROR("failed jtag scan: %d", retval);
return retval;
}
- /* Always return to dbus. */
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
uint32_t in = buf_get_u32(field.in_value, 0, 32);
LOG_DEBUG("DTMCONTROL: 0x%x -> 0x%x", out, in);
@@ -390,1067 +250,21 @@ static uint32_t idcode_scan(struct target *target)
return in;
}
-static void increase_dbus_busy_delay(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- info->dbus_busy_delay += info->dbus_busy_delay / 10 + 1;
- LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
- info->dtmcontrol_idle, info->dbus_busy_delay,
- info->interrupt_high_delay);
-
- dtmcontrol_scan(target, DTMCONTROL_DBUS_RESET);
-}
-
-static void increase_interrupt_high_delay(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- info->interrupt_high_delay += info->interrupt_high_delay / 10 + 1;
- LOG_INFO("dtmcontrol_idle=%d, dbus_busy_delay=%d, interrupt_high_delay=%d",
- info->dtmcontrol_idle, info->dbus_busy_delay,
- info->interrupt_high_delay);
-}
-
-static void add_dbus_scan(const struct target *target, struct scan_field *field,
- uint8_t *out_value, uint8_t *in_value, dbus_op_t op,
- uint16_t address, uint64_t data)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- field->num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE;
- field->in_value = in_value;
- field->out_value = out_value;
-
- buf_set_u64(out_value, DBUS_OP_START, DBUS_OP_SIZE, op);
- buf_set_u64(out_value, DBUS_DATA_START, DBUS_DATA_SIZE, data);
- buf_set_u64(out_value, DBUS_ADDRESS_START, info->addrbits, address);
-
- jtag_add_dr_scan(target->tap, 1, field, TAP_IDLE);
-
- int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
- if (data & DMCONTROL_INTERRUPT) {
- idle_count += info->interrupt_high_delay;
- }
-
- if (idle_count) {
- jtag_add_runtest(idle_count, TAP_IDLE);
- }
-}
-
-static void dump_field(const struct scan_field *field)
-{
- static const char *op_string[] = {"nop", "r", "w", "?"};
- static const char *status_string[] = {"+", "?", "F", "b"};
-
- if (debug_level < LOG_LVL_DEBUG)
- return;
-
- uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
- unsigned int out_op = (out >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
- char out_interrupt = ((out >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
- char out_haltnot = ((out >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
- unsigned int out_data = out >> 2;
- unsigned int out_address = out >> DBUS_ADDRESS_START;
- uint64_t in = buf_get_u64(field->in_value, 0, field->num_bits);
- unsigned int in_op = (in >> DBUS_OP_START) & ((1 << DBUS_OP_SIZE) - 1);
- char in_interrupt = ((in >> DBUS_DATA_START) & DMCONTROL_INTERRUPT) ? 'i' : '.';
- char in_haltnot = ((in >> DBUS_DATA_START) & DMCONTROL_HALTNOT) ? 'h' : '.';
- unsigned int in_data = in >> 2;
- unsigned int in_address = in >> DBUS_ADDRESS_START;
-
- log_printf_lf(LOG_LVL_DEBUG,
- __FILE__, __LINE__, "scan",
- "%db %s %c%c:%08x @%02x -> %s %c%c:%08x @%02x",
- field->num_bits,
- op_string[out_op], out_interrupt, out_haltnot, out_data,
- out_address,
- status_string[in_op], in_interrupt, in_haltnot, in_data,
- in_address);
-}
-
-static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
- uint64_t *data_in, dbus_op_t op, uint16_t address_out, uint64_t data_out)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- uint8_t in[8] = {0};
- uint8_t out[8];
- struct scan_field field = {
- .num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
- .out_value = out,
- .in_value = in
- };
-
- assert(info->addrbits != 0);
-
- buf_set_u64(out, DBUS_OP_START, DBUS_OP_SIZE, op);
- buf_set_u64(out, DBUS_DATA_START, DBUS_DATA_SIZE, data_out);
- buf_set_u64(out, DBUS_ADDRESS_START, info->addrbits, address_out);
-
- /* Assume dbus is already selected. */
- jtag_add_dr_scan(target->tap, 1, &field, TAP_IDLE);
-
- int idle_count = info->dtmcontrol_idle + info->dbus_busy_delay;
-
- if (idle_count) {
- jtag_add_runtest(idle_count, TAP_IDLE);
- }
-
- int retval = jtag_execute_queue();
- if (retval != ERROR_OK) {
- LOG_ERROR("dbus_scan failed jtag scan");
- return retval;
- }
-
- if (data_in) {
- *data_in = buf_get_u64(in, DBUS_DATA_START, DBUS_DATA_SIZE);
- }
-
- if (address_in) {
- *address_in = buf_get_u32(in, DBUS_ADDRESS_START, info->addrbits);
- }
-
- dump_field(&field);
-
- return buf_get_u32(in, DBUS_OP_START, DBUS_OP_SIZE);
-}
-
-static uint64_t dbus_read(struct target *target, uint16_t address)
-{
- uint64_t value;
- dbus_status_t status;
- uint16_t address_in;
-
- unsigned i = 0;
- do {
- status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, address, 0);
- if (status == DBUS_STATUS_BUSY) {
- increase_dbus_busy_delay(target);
- }
- } while (((status == DBUS_STATUS_BUSY) || (address_in != address)) &&
- i++ < 256);
-
- if (status != DBUS_STATUS_SUCCESS) {
- LOG_ERROR("failed read from 0x%x; value=0x%" PRIx64 ", status=%d\n", address, value, status);
- }
-
- return value;
-}
-
-static void dbus_write(struct target *target, uint16_t address, uint64_t value)
-{
- dbus_status_t status = DBUS_STATUS_BUSY;
- unsigned i = 0;
- while (status == DBUS_STATUS_BUSY && i++ < 256) {
- status = dbus_scan(target, NULL, NULL, DBUS_OP_WRITE, address, value);
- if (status == DBUS_STATUS_BUSY) {
- increase_dbus_busy_delay(target);
- }
- }
- if (status != DBUS_STATUS_SUCCESS) {
- LOG_ERROR("failed to write 0x%" PRIx64 " to 0x%x; status=%d\n", value, address, status);
- }
-}
-
-/*** scans "class" ***/
-
-typedef struct {
- // Number of scans that space is reserved for.
- unsigned int scan_count;
- // Size reserved in memory for each scan, in bytes.
- unsigned int scan_size;
- unsigned int next_scan;
- uint8_t *in;
- uint8_t *out;
- struct scan_field *field;
- const struct target *target;
-} scans_t;
-
-static scans_t *scans_new(struct target *target, unsigned int scan_count)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- scans_t *scans = malloc(sizeof(scans_t));
- scans->scan_count = scan_count;
- // This code also gets called before xlen is detected.
- if (info->xlen)
- scans->scan_size = 2 + info->xlen / 8;
- else
- scans->scan_size = 2 + 128 / 8;
- scans->next_scan = 0;
- scans->in = calloc(scans->scan_size, scans->scan_count);
- scans->out = calloc(scans->scan_size, scans->scan_count);
- scans->field = calloc(scans->scan_count, sizeof(struct scan_field));
- scans->target = target;
- return scans;
-}
-
-static scans_t *scans_delete(scans_t *scans)
-{
- assert(scans);
- free(scans->field);
- free(scans->out);
- free(scans->in);
- free(scans);
- return NULL;
-}
-
-static void scans_reset(scans_t *scans)
-{
- scans->next_scan = 0;
-}
-
-static void scans_dump(scans_t *scans)
-{
- for (unsigned int i = 0; i < scans->next_scan; i++) {
- dump_field(&scans->field[i]);
- }
-}
-
-static int scans_execute(scans_t *scans)
-{
- int retval = jtag_execute_queue();
- if (retval != ERROR_OK) {
- LOG_ERROR("failed jtag scan: %d", retval);
- return retval;
- }
-
- scans_dump(scans);
-
- return ERROR_OK;
-}
-
-/** Add a 32-bit dbus write to the scans structure. */
-static void scans_add_write32(scans_t *scans, uint16_t address, uint32_t data,
- bool set_interrupt)
-{
- const unsigned int i = scans->next_scan;
- int data_offset = scans->scan_size * i;
- add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
- scans->in + data_offset, DBUS_OP_WRITE, address,
- (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT | data);
- scans->next_scan++;
- assert(scans->next_scan <= scans->scan_count);
-}
-
-/** Add a 32-bit dbus write for an instruction that jumps to the beginning of
- * debug RAM. */
-static void scans_add_write_jump(scans_t *scans, uint16_t address,
- bool set_interrupt)
-{
- scans_add_write32(scans, address,
- jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*address))),
- set_interrupt);
-}
-
-/** Add a 32-bit dbus write for an instruction that loads from the indicated
- * slot. */
-static void scans_add_write_load(scans_t *scans, uint16_t address,
- unsigned int reg, slot_t slot, bool set_interrupt)
-{
- scans_add_write32(scans, address, load_slot(scans->target, reg, slot),
- set_interrupt);
-}
-
-/** Add a 32-bit dbus write for an instruction that stores to the indicated
- * slot. */
-static void scans_add_write_store(scans_t *scans, uint16_t address,
- unsigned int reg, slot_t slot, bool set_interrupt)
-{
- scans_add_write32(scans, address, store_slot(scans->target, reg, slot),
- set_interrupt);
-}
-
-/** Add a 32-bit dbus read. */
-static void scans_add_read32(scans_t *scans, uint16_t address, bool set_interrupt)
-{
- assert(scans->next_scan < scans->scan_count);
- const unsigned int i = scans->next_scan;
- int data_offset = scans->scan_size * i;
- add_dbus_scan(scans->target, &scans->field[i], scans->out + data_offset,
- scans->in + data_offset, DBUS_OP_READ, address,
- (set_interrupt ? DMCONTROL_INTERRUPT : 0) | DMCONTROL_HALTNOT);
- scans->next_scan++;
-}
-
-/** Add one or more scans to read the indicated slot. */
-static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
-{
- const struct target *target = scans->target;
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- switch (info->xlen) {
- case 32:
- scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
- break;
- case 64:
- scans_add_read32(scans, slot_offset(target, slot), false);
- scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
- break;
- }
-}
-
-static uint32_t scans_get_u32(scans_t *scans, unsigned int index,
- unsigned first, unsigned num)
-{
- return buf_get_u32(scans->in + scans->scan_size * index, first, num);
-}
-
-static uint64_t scans_get_u64(scans_t *scans, unsigned int index,
- unsigned first, unsigned num)
-{
- return buf_get_u64(scans->in + scans->scan_size * index, first, num);
-}
-
-/*** end of scans class ***/
-
-static uint32_t dram_read32(struct target *target, unsigned int index)
-{
- uint16_t address = dram_address(index);
- uint32_t value = dbus_read(target, address);
- return value;
-}
-
-static void dram_write32(struct target *target, unsigned int index, uint32_t value,
- bool set_interrupt)
-{
- uint64_t dbus_value = DMCONTROL_HALTNOT | value;
- if (set_interrupt)
- dbus_value |= DMCONTROL_INTERRUPT;
- dbus_write(target, dram_address(index), dbus_value);
-}
-
-/** Read the haltnot and interrupt bits. */
-static bits_t read_bits(struct target *target)
-{
- uint64_t value;
- dbus_status_t status;
- uint16_t address_in;
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- bits_t err_result = {
- .haltnot = 0,
- .interrupt = 0
- };
-
- do {
- unsigned i = 0;
- do {
- status = dbus_scan(target, &address_in, &value, DBUS_OP_READ, 0, 0);
- if (status == DBUS_STATUS_BUSY) {
- if (address_in == (1<<info->addrbits) - 1 &&
- value == (1ULL<<DBUS_DATA_SIZE) - 1) {
- LOG_ERROR("TDO seems to be stuck high.");
- return err_result;
- }
- increase_dbus_busy_delay(target);
- }
- } while (status == DBUS_STATUS_BUSY && i++ < 256);
-
- if (i >= 256) {
- LOG_ERROR("Failed to read from 0x%x; status=%d", address_in, status);
- return err_result;
- }
- } while (address_in > 0x10 && address_in != DMCONTROL);
-
- bits_t result = {
- .haltnot = get_field(value, DMCONTROL_HALTNOT),
- .interrupt = get_field(value, DMCONTROL_INTERRUPT)
- };
- return result;
-}
-
-static int wait_for_debugint_clear(struct target *target, bool ignore_first)
-{
- time_t start = time(NULL);
- if (ignore_first) {
- // Throw away the results of the first read, since they'll contain the
- // result of the read that happened just before debugint was set.
- // (Assuming the last scan before calling this function was one that
- // sets debugint.)
- read_bits(target);
- }
- while (1) {
- bits_t bits = read_bits(target);
- if (!bits.interrupt) {
- return ERROR_OK;
- }
- if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
- LOG_ERROR("Timed out waiting for debug int to clear.");
- return ERROR_FAIL;
- }
- }
-}
-
-static int dram_check32(struct target *target, unsigned int index,
- uint32_t expected)
-{
- uint16_t address = dram_address(index);
- uint32_t actual = dbus_read(target, address);
- if (expected != actual) {
- LOG_ERROR("Wrote 0x%x to Debug RAM at %d, but read back 0x%x",
- expected, index, actual);
- return ERROR_FAIL;
- }
- return ERROR_OK;
-}
-
-static void cache_set32(struct target *target, unsigned int index, uint32_t data)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- if (info->dram_cache[index].valid &&
- info->dram_cache[index].data == data) {
- // This is already preset on the target.
- LOG_DEBUG("cache[0x%x] = 0x%x (hit)", index, data);
- return;
- }
- LOG_DEBUG("cache[0x%x] = 0x%x", index, data);
- info->dram_cache[index].data = data;
- info->dram_cache[index].valid = true;
- info->dram_cache[index].dirty = true;
-}
-
-static void cache_set(struct target *target, slot_t slot, uint64_t data)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- unsigned int offset = slot_offset(target, slot);
- cache_set32(target, offset, data);
- if (info->xlen > 32) {
- cache_set32(target, offset + 1, data >> 32);
- }
-}
-
-static void cache_set_jump(struct target *target, unsigned int index)
-{
- cache_set32(target, index,
- jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
-}
-
-static void cache_set_load(struct target *target, unsigned int index,
- unsigned int reg, slot_t slot)
-{
- uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
- cache_set32(target, index, load(target, reg, ZERO, offset));
-}
-
-static void cache_set_store(struct target *target, unsigned int index,
- unsigned int reg, slot_t slot)
-{
- uint16_t offset = DEBUG_RAM_START + 4 * slot_offset(target, slot);
- cache_set32(target, index, store(target, reg, ZERO, offset));
-}
-
-static void dump_debug_ram(struct target *target)
-{
- for (unsigned int i = 0; i < DRAM_CACHE_SIZE; i++) {
- uint32_t value = dram_read32(target, i);
- LOG_ERROR("Debug RAM 0x%x: 0x%08x", i, value);
- }
-}
-
-/* Call this if the code you just ran writes to debug RAM entries 0 through 3. */
-static void cache_invalidate(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- for (unsigned int i = 0; i < info->dramsize; i++) {
- info->dram_cache[i].valid = false;
- info->dram_cache[i].dirty = false;
- }
-}
-
-/* Called by cache_write() after the program has run. Also call this if you're
- * running programs without calling cache_write(). */
-static void cache_clean(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- for (unsigned int i = 0; i < info->dramsize; i++) {
- if (i >= 4) {
- info->dram_cache[i].valid = false;
- }
- info->dram_cache[i].dirty = false;
- }
-}
-
-static int cache_check(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- int error = 0;
-
- for (unsigned int i = 0; i < info->dramsize; i++) {
- if (info->dram_cache[i].valid && !info->dram_cache[i].dirty) {
- if (dram_check32(target, i, info->dram_cache[i].data) != ERROR_OK) {
- error++;
- }
- }
- }
-
- if (error) {
- dump_debug_ram(target);
- return ERROR_FAIL;
- }
-
- return ERROR_OK;
-}
-
-/** Write cache to the target, and optionally run the program.
- * Then read the value at address into the cache, assuming address < 128. */
-#define CACHE_NO_READ 128
-static int cache_write(struct target *target, unsigned int address, bool run)
-{
- LOG_DEBUG("enter");
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- scans_t *scans = scans_new(target, info->dramsize + 2);
-
- unsigned int last = info->dramsize;
- for (unsigned int i = 0; i < info->dramsize; i++) {
- if (info->dram_cache[i].dirty) {
- last = i;
- }
- }
-
- if (last == info->dramsize) {
- // Nothing needs to be written to RAM.
- dbus_write(target, DMCONTROL, DMCONTROL_HALTNOT | DMCONTROL_INTERRUPT);
-
- } else {
- for (unsigned int i = 0; i < info->dramsize; i++) {
- if (info->dram_cache[i].dirty) {
- bool set_interrupt = (i == last && run);
- scans_add_write32(scans, i, info->dram_cache[i].data,
- set_interrupt);
- }
- }
- }
-
- if (run || address < CACHE_NO_READ) {
- // Throw away the results of the first read, since it'll contain the
- // result of the read that happened just before debugint was set.
- scans_add_read32(scans, address, false);
-
- // This scan contains the results of the read the caller requested, as
- // well as an interrupt bit worth looking at.
- scans_add_read32(scans, address, false);
- }
-
- int retval = scans_execute(scans);
- if (retval != ERROR_OK) {
- LOG_ERROR("JTAG execute failed.");
- return retval;
- }
-
- int errors = 0;
- for (unsigned int i = 0; i < scans->next_scan; i++) {
- dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
- DBUS_OP_SIZE);
- switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- return ERROR_FAIL;
- case DBUS_STATUS_BUSY:
- errors++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
- }
- }
-
- if (errors) {
- increase_dbus_busy_delay(target);
-
- // Try again, using the slow careful code.
- // Write all RAM, just to be extra cautious.
- for (unsigned int i = 0; i < info->dramsize; i++) {
- if (i == last && run) {
- dram_write32(target, last, info->dram_cache[last].data, true);
- } else {
- dram_write32(target, i, info->dram_cache[i].data, false);
- }
- info->dram_cache[i].dirty = false;
- }
- if (run) {
- cache_clean(target);
- }
-
- if (wait_for_debugint_clear(target, true) != ERROR_OK) {
- LOG_ERROR("Debug interrupt didn't clear.");
- dump_debug_ram(target);
- return ERROR_FAIL;
- }
-
- } else {
- if (run) {
- cache_clean(target);
- } else {
- for (unsigned int i = 0; i < info->dramsize; i++) {
- info->dram_cache[i].dirty = false;
- }
- }
-
- if (run || address < CACHE_NO_READ) {
- int interrupt = scans_get_u32(scans, scans->next_scan-1,
- DBUS_DATA_START + 33, 1);
- if (interrupt) {
- increase_interrupt_high_delay(target);
- // Slow path wait for it to clear.
- if (wait_for_debugint_clear(target, false) != ERROR_OK) {
- LOG_ERROR("Debug interrupt didn't clear.");
- dump_debug_ram(target);
- return ERROR_FAIL;
- }
- } else {
- // We read a useful value in that last scan.
- unsigned int read_addr = scans_get_u32(scans, scans->next_scan-1,
- DBUS_ADDRESS_START, info->addrbits);
- if (read_addr != address) {
- LOG_INFO("Got data from 0x%x but expected it from 0x%x",
- read_addr, address);
- }
- info->dram_cache[read_addr].data =
- scans_get_u32(scans, scans->next_scan-1, DBUS_DATA_START, 32);
- info->dram_cache[read_addr].valid = true;
- }
- }
- }
-
- scans_delete(scans);
- LOG_DEBUG("exit");
-
- return ERROR_OK;
-}
-
-uint32_t cache_get32(struct target *target, unsigned int address)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- if (!info->dram_cache[address].valid) {
- info->dram_cache[address].data = dram_read32(target, address);
- info->dram_cache[address].valid = true;
- }
- return info->dram_cache[address].data;
-}
-
-uint64_t cache_get(struct target *target, slot_t slot)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- unsigned int offset = slot_offset(target, slot);
- uint64_t value = cache_get32(target, offset);
- if (info->xlen > 32) {
- value |= ((uint64_t) cache_get32(target, offset + 1)) << 32;
- }
- return value;
-}
-
-/* Write instruction that jumps from the specified word in Debug RAM to resume
- * in Debug ROM. */
-static void dram_write_jump(struct target *target, unsigned int index,
- bool set_interrupt)
-{
- dram_write32(target, index,
- jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))),
- set_interrupt);
-}
-
-static int wait_for_state(struct target *target, enum target_state state)
-{
- time_t start = time(NULL);
- while (1) {
- int result = riscv_poll(target);
- if (result != ERROR_OK) {
- return result;
- }
- if (target->state == state) {
- return ERROR_OK;
- }
- if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
- LOG_ERROR("Timed out waiting for state %d.", state);
- return ERROR_FAIL;
- }
- }
-}
-
-static int read_csr(struct target *target, uint64_t *value, uint32_t csr)
-{
- cache_set32(target, 0, csrr(S0, csr));
- cache_set_store(target, 1, S0, SLOT0);
- cache_set_jump(target, 2);
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
- *value = cache_get(target, SLOT0);
- LOG_DEBUG("csr 0x%x = 0x%" PRIx64, csr, *value);
-
- return ERROR_OK;
-}
-
-static int write_csr(struct target *target, uint32_t csr, uint64_t value)
-{
- LOG_DEBUG("csr 0x%x <- 0x%" PRIx64, csr, value);
- cache_set_load(target, 0, S0, SLOT0);
- cache_set32(target, 1, csrw(S0, csr));
- cache_set_jump(target, 2);
- cache_set(target, SLOT0, value);
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- return ERROR_OK;
-}
-
-static int write_gpr(struct target *target, unsigned int gpr, uint64_t value)
-{
- cache_set_load(target, 0, gpr, SLOT0);
- cache_set_jump(target, 1);
- cache_set(target, SLOT0, value);
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
- return ERROR_OK;
-}
-
-static int maybe_read_tselect(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- if (info->tselect_dirty) {
- int result = read_csr(target, &info->tselect, CSR_TSELECT);
- if (result != ERROR_OK)
- return result;
- info->tselect_dirty = false;
- }
-
- return ERROR_OK;
-}
-
-static int maybe_write_tselect(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- if (!info->tselect_dirty) {
- int result = write_csr(target, CSR_TSELECT, info->tselect);
- if (result != ERROR_OK)
- return result;
- info->tselect_dirty = true;
- }
-
- return ERROR_OK;
-}
-
-static int execute_resume(struct target *target, bool step)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- LOG_DEBUG("step=%d", step);
-
- maybe_write_tselect(target);
-
- // TODO: check if dpc is dirty (which also is true if an exception was hit
- // at any time)
- cache_set_load(target, 0, S0, SLOT0);
- cache_set32(target, 1, csrw(S0, CSR_DPC));
- cache_set_jump(target, 2);
- cache_set(target, SLOT0, info->dpc);
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
- if (mstatus_reg->valid) {
- uint64_t mstatus_user = buf_get_u64(mstatus_reg->value, 0, info->xlen);
- if (mstatus_user != info->mstatus_actual) {
- cache_set_load(target, 0, S0, SLOT0);
- cache_set32(target, 1, csrw(S0, CSR_MSTATUS));
- cache_set_jump(target, 2);
- cache_set(target, SLOT0, mstatus_user);
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
- }
- }
-
- info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS | DCSR_EBREAKU;
- info->dcsr &= ~DCSR_HALT;
-
- if (step) {
- info->dcsr |= DCSR_STEP;
- } else {
- info->dcsr &= ~DCSR_STEP;
- }
-
- dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
- dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
- dram_write32(target, 2, fence_i(), false);
- dram_write_jump(target, 3, false);
-
- // Write DCSR value, set interrupt and clear haltnot.
- uint64_t dbus_value = DMCONTROL_INTERRUPT | info->dcsr;
- dbus_write(target, dram_address(4), dbus_value);
-
- cache_invalidate(target);
-
- if (wait_for_debugint_clear(target, true) != ERROR_OK) {
- LOG_ERROR("Debug interrupt didn't clear.");
- return ERROR_FAIL;
- }
-
- target->state = TARGET_RUNNING;
- register_cache_invalidate(target->reg_cache);
-
- return ERROR_OK;
-}
-
-// Execute a step, and wait for reentry into Debug Mode.
-static int full_step(struct target *target, bool announce)
-{
- int result = execute_resume(target, true);
- if (result != ERROR_OK)
- return result;
- time_t start = time(NULL);
- while (1) {
- result = poll_target(target, announce);
- if (result != ERROR_OK)
- return result;
- if (target->state != TARGET_DEBUG_RUNNING)
- break;
- if (time(NULL) - start > WALL_CLOCK_TIMEOUT) {
- LOG_ERROR("Timed out waiting for step to complete.");
- return ERROR_FAIL;
- }
- }
- return ERROR_OK;
-}
-
-static int resume(struct target *target, int debug_execution, bool step)
-{
- if (debug_execution) {
- LOG_ERROR("TODO: debug_execution is true");
- return ERROR_FAIL;
- }
-
- return execute_resume(target, step);
-}
-
-/** Update register sizes based on xlen. */
-static void update_reg_list(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- if (info->reg_values) {
- free(info->reg_values);
- }
- info->reg_values = malloc(REG_COUNT * info->xlen / 4);
-
- for (unsigned int i = 0; i < REG_COUNT; i++) {
- struct reg *r = &target->reg_cache->reg_list[i];
- r->value = info->reg_values + i * info->xlen / 4;
- if (r->dirty) {
- LOG_ERROR("Register %d was dirty. Its value is lost.", i);
- }
- if (i == REG_PRIV) {
- r->size = 8;
- } else {
- r->size = info->xlen;
- }
- r->valid = false;
- }
-}
-
-static uint64_t reg_cache_get(struct target *target, unsigned int number)
-{
- struct reg *r = &target->reg_cache->reg_list[number];
- if (!r->valid) {
- LOG_ERROR("Register cache entry for %d is invalid!", number);
- assert(r->valid);
- }
- uint64_t value = buf_get_u64(r->value, 0, r->size);
- LOG_DEBUG("%s = 0x%" PRIx64, r->name, value);
- return value;
-}
-
-static void reg_cache_set(struct target *target, unsigned int number,
- uint64_t value)
-{
- struct reg *r = &target->reg_cache->reg_list[number];
- LOG_DEBUG("%s <= 0x%" PRIx64, r->name, value);
- r->valid = true;
- buf_set_u64(r->value, 0, r->size, value);
-}
-
-static int update_mstatus_actual(struct target *target)
-{
- struct reg *mstatus_reg = &target->reg_cache->reg_list[REG_MSTATUS];
- if (mstatus_reg->valid) {
- // We previously made it valid.
- return ERROR_OK;
- }
-
- // Force reading the register. In that process mstatus_actual will be
- // updated.
- return register_get(&target->reg_cache->reg_list[REG_MSTATUS]);
-}
-
-/*** OpenOCD target functions. ***/
-
-static int register_get(struct reg *reg)
+static struct target_type *get_target_type(struct target *target)
{
- struct target *target = (struct target *) reg->arch_info;
riscv_info_t *info = (riscv_info_t *) target->arch_info;
- maybe_write_tselect(target);
-
- if (reg->number <= REG_XPR31) {
- buf_set_u64(reg->value, 0, info->xlen, reg_cache_get(target, reg->number));
- LOG_DEBUG("%s=0x%" PRIx64, reg->name, reg_cache_get(target, reg->number));
- return ERROR_OK;
- } else if (reg->number == REG_PC) {
- buf_set_u32(reg->value, 0, 32, info->dpc);
- reg->valid = true;
- LOG_DEBUG("%s=0x%" PRIx64 " (cached)", reg->name, info->dpc);
- return ERROR_OK;
- } else if (reg->number >= REG_FPR0 && reg->number <= REG_FPR31) {
- int result = update_mstatus_actual(target);
- if (result != ERROR_OK) {
- return result;
- }
- unsigned i = 0;
- if ((info->mstatus_actual & MSTATUS_FS) == 0) {
- info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
- cache_set_load(target, i++, S0, SLOT1);
- cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
- cache_set(target, SLOT1, info->mstatus_actual);
- }
-
- if (info->xlen == 32) {
- cache_set32(target, i++, fsw(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
- } else {
- cache_set32(target, i++, fsd(reg->number - REG_FPR0, 0, DEBUG_RAM_START + 16));
- }
- cache_set_jump(target, i++);
- } else if (reg->number >= REG_CSR0 && reg->number <= REG_CSR4095) {
- cache_set32(target, 0, csrr(S0, reg->number - REG_CSR0));
- cache_set_store(target, 1, S0, SLOT0);
- cache_set_jump(target, 2);
- } else if (reg->number == REG_PRIV) {
- buf_set_u64(reg->value, 0, 8, get_field(info->dcsr, DCSR_PRV));
- LOG_DEBUG("%s=%d (cached)", reg->name,
- (int) get_field(info->dcsr, DCSR_PRV));
- return ERROR_OK;
- } else {
- LOG_ERROR("Don't know how to read register %d (%s)", reg->number, reg->name);
- return ERROR_FAIL;
- }
-
- if (cache_write(target, 4, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- uint32_t exception = cache_get32(target, info->dramsize-1);
- if (exception) {
- LOG_ERROR("Got exception 0x%x when reading register %d", exception,
- reg->number);
- buf_set_u64(reg->value, 0, info->xlen, ~0);
- return ERROR_FAIL;
- }
-
- uint64_t value = cache_get(target, SLOT0);
- LOG_DEBUG("%s=0x%" PRIx64, reg->name, value);
- buf_set_u64(reg->value, 0, info->xlen, value);
-
- if (reg->number == REG_MSTATUS) {
- info->mstatus_actual = value;
- reg->valid = true;
- }
-
- return ERROR_OK;
-}
-
-static int register_write(struct target *target, unsigned int number,
- uint64_t value)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- maybe_write_tselect(target);
-
- if (number == S0) {
- cache_set_load(target, 0, S0, SLOT0);
- cache_set32(target, 1, csrw(S0, CSR_DSCRATCH));
- cache_set_jump(target, 2);
- } else if (number == S1) {
- cache_set_load(target, 0, S0, SLOT0);
- cache_set_store(target, 1, S0, SLOT_LAST);
- cache_set_jump(target, 2);
- } else if (number <= REG_XPR31) {
- cache_set_load(target, 0, number - REG_XPR0, SLOT0);
- cache_set_jump(target, 1);
- } else if (number == REG_PC) {
- info->dpc = value;
- return ERROR_OK;
- } else if (number >= REG_FPR0 && number <= REG_FPR31) {
- int result = update_mstatus_actual(target);
- if (result != ERROR_OK) {
- return result;
- }
- unsigned i = 0;
- if ((info->mstatus_actual & MSTATUS_FS) == 0) {
- info->mstatus_actual = set_field(info->mstatus_actual, MSTATUS_FS, 1);
- cache_set_load(target, i++, S0, SLOT1);
- cache_set32(target, i++, csrw(S0, CSR_MSTATUS));
- cache_set(target, SLOT1, info->mstatus_actual);
- }
-
- if (info->xlen == 32) {
- cache_set32(target, i++, flw(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
- } else {
- cache_set32(target, i++, fld(number - REG_FPR0, 0, DEBUG_RAM_START + 16));
- }
- cache_set_jump(target, i++);
- } else if (number >= REG_CSR0 && number <= REG_CSR4095) {
- cache_set_load(target, 0, S0, SLOT0);
- cache_set32(target, 1, csrw(S0, number - REG_CSR0));
- cache_set_jump(target, 2);
-
- if (number == REG_MSTATUS) {
- info->mstatus_actual = value;
- }
- } else if (number == REG_PRIV) {
- info->dcsr = set_field(info->dcsr, DCSR_PRV, value);
- return ERROR_OK;
- } else {
- LOG_ERROR("Don't know how to write register %d", number);
- return ERROR_FAIL;
- }
-
- cache_set(target, SLOT0, value);
- if (cache_write(target, info->dramsize - 1, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- uint32_t exception = cache_get32(target, info->dramsize-1);
- if (exception) {
- LOG_ERROR("Got exception 0x%x when writing register %d", exception,
- number);
- return ERROR_FAIL;
+ switch (info->dtm_version) {
+ case 0:
+ return &riscv011_target;
+ case 1:
+ return &riscv013_target;
+ default:
+ LOG_ERROR("Unsupported DTM version: %d", info->dtm_version);
+ return NULL;
}
-
- return ERROR_OK;
-}
-
-static int register_set(struct reg *reg, uint8_t *buf)
-{
- struct target *target = (struct target *) reg->arch_info;
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- uint64_t value = buf_get_u64(buf, 0, info->xlen);
-
- LOG_DEBUG("write 0x%" PRIx64 " to %s", value, reg->name);
- struct reg *r = &target->reg_cache->reg_list[reg->number];
- r->valid = true;
- memcpy(r->value, buf, (r->size + 7) / 8);
-
- return register_write(target, reg->number, value);
}
-static struct reg_arch_type riscv_reg_arch_type = {
- .get = register_get,
- .set = register_set
-};
-
static int riscv_init_target(struct command_context *cmd_ctx,
struct target *target)
{
@@ -1459,58 +273,20 @@ static int riscv_init_target(struct command_context *cmd_ctx,
if (!target->arch_info)
return ERROR_FAIL;
riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ info->cmd_ctx = cmd_ctx;
select_dtmcontrol.num_bits = target->tap->ir_length;
select_dbus.num_bits = target->tap->ir_length;
select_idcode.num_bits = target->tap->ir_length;
- target->reg_cache = calloc(1, sizeof(*target->reg_cache));
- target->reg_cache->name = "RISC-V registers";
- target->reg_cache->num_regs = REG_COUNT;
-
- target->reg_cache->reg_list = calloc(REG_COUNT, sizeof(struct reg));
-
- const unsigned int max_reg_name_len = 12;
- info->reg_names = calloc(1, REG_COUNT * max_reg_name_len);
- char *reg_name = info->reg_names;
- info->reg_values = NULL;
-
- for (unsigned int i = 0; i < REG_COUNT; i++) {
- struct reg *r = &target->reg_cache->reg_list[i];
- r->number = i;
- r->caller_save = true;
- r->dirty = false;
- r->valid = false;
- r->exist = true;
- r->type = &riscv_reg_arch_type;
- r->arch_info = target;
- if (i <= REG_XPR31) {
- sprintf(reg_name, "x%d", i);
- } else if (i == REG_PC) {
- sprintf(reg_name, "pc");
- } else if (i >= REG_FPR0 && i <= REG_FPR31) {
- sprintf(reg_name, "f%d", i - REG_FPR0);
- } else if (i >= REG_CSR0 && i <= REG_CSR4095) {
- sprintf(reg_name, "csr%d", i - REG_CSR0);
- } else if (i == REG_PRIV) {
- sprintf(reg_name, "priv");
- }
- if (reg_name[0]) {
- r->name = reg_name;
- }
- reg_name += strlen(reg_name) + 1;
- assert(reg_name < info->reg_names + REG_COUNT * max_reg_name_len);
- }
- update_reg_list(target);
-
- memset(info->trigger_unique_id, 0xff, sizeof(info->trigger_unique_id));
-
return ERROR_OK;
}
static void riscv_deinit_target(struct target *target)
{
LOG_DEBUG("riscv_deinit_target()");
+ struct target_type *tt = get_target_type(target);
+ tt->deinit_target(target);
riscv_info_t *info = (riscv_info_t *) target->arch_info;
free(info);
target->arch_info = NULL;
@@ -1518,315 +294,43 @@ static void riscv_deinit_target(struct target *target)
static int riscv_halt(struct target *target)
{
- LOG_DEBUG("riscv_halt()");
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- cache_set32(target, 0, csrsi(CSR_DCSR, DCSR_HALT));
- cache_set32(target, 1, csrr(S0, CSR_MHARTID));
- cache_set32(target, 2, sw(S0, ZERO, SETHALTNOT));
- cache_set_jump(target, 3);
-
- if (cache_write(target, 4, true) != ERROR_OK) {
- LOG_ERROR("cache_write() failed.");
- return ERROR_FAIL;
- }
-
- return ERROR_OK;
-}
-
-static int add_trigger(struct target *target, struct trigger *trigger)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- maybe_read_tselect(target);
-
- unsigned int i;
- for (i = 0; i < info->trigger_count; i++) {
- if (info->trigger_unique_id[i] != -1) {
- continue;
- }
-
- write_csr(target, CSR_TSELECT, i);
-
- uint64_t tdata1;
- read_csr(target, &tdata1, CSR_TDATA1);
- int type = get_field(tdata1, MCONTROL_TYPE(info->xlen));
-
- if (type != 2) {
- continue;
- }
-
- if (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD)) {
- // Trigger is already in use, presumably by user code.
- continue;
- }
-
- // address/data match trigger
- tdata1 |= MCONTROL_DMODE(info->xlen);
- tdata1 = set_field(tdata1, MCONTROL_ACTION,
- MCONTROL_ACTION_DEBUG_MODE);
- tdata1 = set_field(tdata1, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
- tdata1 |= MCONTROL_M;
- if (info->misa & (1 << ('H' - 'A')))
- tdata1 |= MCONTROL_H;
- if (info->misa & (1 << ('S' - 'A')))
- tdata1 |= MCONTROL_S;
- if (info->misa & (1 << ('U' - 'A')))
- tdata1 |= MCONTROL_U;
-
- if (trigger->execute)
- tdata1 |= MCONTROL_EXECUTE;
- if (trigger->read)
- tdata1 |= MCONTROL_LOAD;
- if (trigger->write)
- tdata1 |= MCONTROL_STORE;
-
- write_csr(target, CSR_TDATA1, tdata1);
-
- uint64_t tdata1_rb;
- read_csr(target, &tdata1_rb, CSR_TDATA1);
- LOG_DEBUG("tdata1=0x%" PRIx64, tdata1_rb);
-
- if (tdata1 != tdata1_rb) {
- LOG_DEBUG("Trigger %d doesn't support what we need; After writing 0x%"
- PRIx64 " to tdata1 it contains 0x%" PRIx64,
- i, tdata1, tdata1_rb);
- write_csr(target, CSR_TDATA1, 0);
- continue;
- }
-
- write_csr(target, CSR_TDATA2, trigger->address);
-
- LOG_DEBUG("Using resource %d for bp %d", i,
- trigger->unique_id);
- info->trigger_unique_id[i] = trigger->unique_id;
- break;
- }
- if (i >= info->trigger_count) {
- LOG_ERROR("Couldn't find an available hardware trigger.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- return ERROR_OK;
-}
-
-static int remove_trigger(struct target *target, struct trigger *trigger)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- maybe_read_tselect(target);
-
- unsigned int i;
- for (i = 0; i < info->trigger_count; i++) {
- if (info->trigger_unique_id[i] == trigger->unique_id) {
- break;
- }
- }
- if (i >= info->trigger_count) {
- LOG_ERROR("Couldn't find the hardware resources used by hardware "
- "trigger.");
- return ERROR_FAIL;
- }
- LOG_DEBUG("Stop using resource %d for bp %d", i, trigger->unique_id);
- write_csr(target, CSR_TSELECT, i);
- write_csr(target, CSR_TDATA1, 0);
- info->trigger_unique_id[i] = -1;
-
- return ERROR_OK;
-}
-
-static void trigger_from_breakpoint(struct trigger *trigger,
- const struct breakpoint *breakpoint)
-{
- trigger->address = breakpoint->address;
- trigger->length = breakpoint->length;
- trigger->mask = ~0LL;
- trigger->read = false;
- trigger->write = false;
- trigger->execute = true;
- // unique_id is unique across both breakpoints and watchpoints.
- trigger->unique_id = breakpoint->unique_id;
-}
-
-static void trigger_from_watchpoint(struct trigger *trigger,
- const struct watchpoint *watchpoint)
-{
- trigger->address = watchpoint->address;
- trigger->length = watchpoint->length;
- trigger->mask = watchpoint->mask;
- trigger->value = watchpoint->value;
- trigger->read = (watchpoint->rw == WPT_READ || watchpoint->rw == WPT_ACCESS);
- trigger->write = (watchpoint->rw == WPT_WRITE || watchpoint->rw == WPT_ACCESS);
- trigger->execute = false;
- // unique_id is unique across both breakpoints and watchpoints.
- trigger->unique_id = watchpoint->unique_id;
+ struct target_type *tt = get_target_type(target);
+ return tt->halt(target);
}
static int riscv_add_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- if (breakpoint->type == BKPT_SOFT) {
- if (target_read_memory(target, breakpoint->address, breakpoint->length, 1,
- breakpoint->orig_instr) != ERROR_OK) {
- LOG_ERROR("Failed to read original instruction at 0x%x",
- breakpoint->address);
- return ERROR_FAIL;
- }
-
- int retval;
- if (breakpoint->length == 4) {
- retval = target_write_u32(target, breakpoint->address, ebreak());
- } else {
- retval = target_write_u16(target, breakpoint->address, ebreak_c());
- }
- if (retval != ERROR_OK) {
- LOG_ERROR("Failed to write %d-byte breakpoint instruction at 0x%x",
- breakpoint->length, breakpoint->address);
- return ERROR_FAIL;
- }
-
- } else if (breakpoint->type == BKPT_HARD) {
- struct trigger trigger;
- trigger_from_breakpoint(&trigger, breakpoint);
- int result = add_trigger(target, &trigger);
- if (result != ERROR_OK) {
- return result;
- }
-
- } else {
- LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- breakpoint->set = true;
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->add_breakpoint(target, breakpoint);
}
static int riscv_remove_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
- if (breakpoint->type == BKPT_SOFT) {
- if (target_write_memory(target, breakpoint->address, breakpoint->length, 1,
- breakpoint->orig_instr) != ERROR_OK) {
- LOG_ERROR("Failed to restore instruction for %d-byte breakpoint at "
- "0x%x", breakpoint->length, breakpoint->address);
- return ERROR_FAIL;
- }
-
- } else if (breakpoint->type == BKPT_HARD) {
- struct trigger trigger;
- trigger_from_breakpoint(&trigger, breakpoint);
- int result = remove_trigger(target, &trigger);
- if (result != ERROR_OK) {
- return result;
- }
-
- } else {
- LOG_INFO("OpenOCD only supports hardware and software breakpoints.");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- breakpoint->set = false;
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->remove_breakpoint(target, breakpoint);
}
static int riscv_add_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- struct trigger trigger;
- trigger_from_watchpoint(&trigger, watchpoint);
-
- int result = add_trigger(target, &trigger);
- if (result != ERROR_OK) {
- return result;
- }
- watchpoint->set = true;
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->add_watchpoint(target, watchpoint);
}
static int riscv_remove_watchpoint(struct target *target,
struct watchpoint *watchpoint)
{
- struct trigger trigger;
- trigger_from_watchpoint(&trigger, watchpoint);
-
- int result = remove_trigger(target, &trigger);
- if (result != ERROR_OK) {
- return result;
- }
- watchpoint->set = false;
-
- return ERROR_OK;
-}
-
-static int strict_step(struct target *target, bool announce)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- LOG_DEBUG("enter");
-
- struct breakpoint *breakpoint = target->breakpoints;
- while (breakpoint) {
- riscv_remove_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-
- struct watchpoint *watchpoint = target->watchpoints;
- while (watchpoint) {
- riscv_remove_watchpoint(target, watchpoint);
- watchpoint = watchpoint->next;
- }
-
- int result = full_step(target, announce);
- if (result != ERROR_OK)
- return result;
-
- breakpoint = target->breakpoints;
- while (breakpoint) {
- riscv_add_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-
- watchpoint = target->watchpoints;
- while (watchpoint) {
- riscv_add_watchpoint(target, watchpoint);
- watchpoint = watchpoint->next;
- }
-
- info->need_strict_step = false;
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->remove_watchpoint(target, watchpoint);
}
static int riscv_step(struct target *target, int current, uint32_t address,
int handle_breakpoints)
{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- if (!current) {
- if (info->xlen > 32) {
- LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
- info->xlen);
- }
- int result = register_write(target, REG_PC, address);
- if (result != ERROR_OK)
- return result;
- }
-
- if (info->need_strict_step || handle_breakpoints) {
- int result = strict_step(target, true);
- if (result != ERROR_OK)
- return result;
- } else {
- return resume(target, 0, true);
- }
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->step(target, current, address, handle_breakpoints);
}
static int riscv_examine(struct target *target)
@@ -1838,775 +342,61 @@ static int riscv_examine(struct target *target)
// Don't need to select dbus, since the first thing we do is read dtmcontrol.
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
uint32_t dtmcontrol = dtmcontrol_scan(target, 0);
LOG_DEBUG("dtmcontrol=0x%x", dtmcontrol);
- LOG_DEBUG(" addrbits=%d", get_field(dtmcontrol, DTMCONTROL_ADDRBITS));
- LOG_DEBUG(" version=%d", get_field(dtmcontrol, DTMCONTROL_VERSION));
- LOG_DEBUG(" idle=%d", get_field(dtmcontrol, DTMCONTROL_IDLE));
- if (dtmcontrol == 0) {
- LOG_ERROR("dtmcontrol is 0. Check JTAG connectivity/board power.");
- return ERROR_FAIL;
- }
- if (get_field(dtmcontrol, DTMCONTROL_VERSION) != 0) {
- LOG_ERROR("Unsupported DTM version %d. (dtmcontrol=0x%x)",
- get_field(dtmcontrol, DTMCONTROL_VERSION), dtmcontrol);
- return ERROR_FAIL;
- }
-
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- info->addrbits = get_field(dtmcontrol, DTMCONTROL_ADDRBITS);
- info->dtmcontrol_idle = get_field(dtmcontrol, DTMCONTROL_IDLE);
- if (info->dtmcontrol_idle == 0) {
- // Some old SiFive cores don't set idle but need it to be 1.
- uint32_t idcode = idcode_scan(target);
- if (idcode == 0x10e31913)
- info->dtmcontrol_idle = 1;
- }
-
- uint32_t dminfo = dbus_read(target, DMINFO);
- LOG_DEBUG("dminfo: 0x%08x", dminfo);
- LOG_DEBUG(" abussize=0x%x", get_field(dminfo, DMINFO_ABUSSIZE));
- LOG_DEBUG(" serialcount=0x%x", get_field(dminfo, DMINFO_SERIALCOUNT));
- LOG_DEBUG(" access128=%d", get_field(dminfo, DMINFO_ACCESS128));
- LOG_DEBUG(" access64=%d", get_field(dminfo, DMINFO_ACCESS64));
- LOG_DEBUG(" access32=%d", get_field(dminfo, DMINFO_ACCESS32));
- LOG_DEBUG(" access16=%d", get_field(dminfo, DMINFO_ACCESS16));
- LOG_DEBUG(" access8=%d", get_field(dminfo, DMINFO_ACCESS8));
- LOG_DEBUG(" dramsize=0x%x", get_field(dminfo, DMINFO_DRAMSIZE));
- LOG_DEBUG(" authenticated=0x%x", get_field(dminfo, DMINFO_AUTHENTICATED));
- LOG_DEBUG(" authbusy=0x%x", get_field(dminfo, DMINFO_AUTHBUSY));
- LOG_DEBUG(" authtype=0x%x", get_field(dminfo, DMINFO_AUTHTYPE));
- LOG_DEBUG(" version=0x%x", get_field(dminfo, DMINFO_VERSION));
-
- if (get_field(dminfo, DMINFO_VERSION) != 1) {
- LOG_ERROR("OpenOCD only supports Debug Module version 1, not %d "
- "(dminfo=0x%x)", get_field(dminfo, DMINFO_VERSION), dminfo);
- return ERROR_FAIL;
- }
-
- info->dramsize = get_field(dminfo, DMINFO_DRAMSIZE) + 1;
+ info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
+ LOG_DEBUG(" version=0x%x", info->dtm_version);
- if (get_field(dminfo, DMINFO_AUTHTYPE) != 0) {
- LOG_ERROR("Authentication required by RISC-V core but not "
- "supported by OpenOCD. dminfo=0x%x", dminfo);
+ struct target_type *tt = get_target_type(target);
+ if (tt == NULL)
return ERROR_FAIL;
- }
-
- // Figure out XLEN, and test writing all of Debug RAM while we're at it.
- cache_set32(target, 0, xori(S1, ZERO, -1));
- // 0xffffffff 0xffffffff:ffffffff 0xffffffff:ffffffff:ffffffff:ffffffff
- cache_set32(target, 1, srli(S1, S1, 31));
- // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START));
- cache_set32(target, 3, srli(S1, S1, 31));
- // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
- cache_set32(target, 4, sw(S1, ZERO, DEBUG_RAM_START + 4));
- cache_set_jump(target, 5);
- for (unsigned i = 6; i < info->dramsize; i++) {
- cache_set32(target, i, i * 0x01020304);
- }
-
- cache_write(target, 0, false);
-
- // Check that we can actually read/write dram.
- if (cache_check(target) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- cache_write(target, 0, true);
- cache_invalidate(target);
-
- uint32_t word0 = cache_get32(target, 0);
- uint32_t word1 = cache_get32(target, 1);
- if (word0 == 1 && word1 == 0) {
- info->xlen = 32;
- } else if (word0 == 0xffffffff && word1 == 3) {
- info->xlen = 64;
- } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
- info->xlen = 128;
- } else {
- uint32_t exception = cache_get32(target, info->dramsize-1);
- LOG_ERROR("Failed to discover xlen; word0=0x%x, word1=0x%x, exception=0x%x",
- word0, word1, exception);
- dump_debug_ram(target);
- return ERROR_FAIL;
- }
- LOG_DEBUG("Discovered XLEN is %d", info->xlen);
-
- // Update register list to match discovered XLEN.
- update_reg_list(target);
- if (read_csr(target, &info->misa, CSR_MISA) != ERROR_OK) {
- LOG_ERROR("Failed to read misa.");
- return ERROR_FAIL;
- }
-
- info->never_halted = true;
-
- int result = riscv_poll(target);
- if (result != ERROR_OK) {
+ int result = tt->init_target(info->cmd_ctx, target);
+ if (result != ERROR_OK)
return result;
- }
-
- target_set_examined(target);
- LOG_INFO("Examined RISCV core; XLEN=%d, misa=0x%" PRIx64, info->xlen, info->misa);
-
- return ERROR_OK;
-}
-
-static riscv_error_t handle_halt_routine(struct target *target)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- scans_t *scans = scans_new(target, 256);
-
- // Read all GPRs as fast as we can, because gdb is going to ask for them
- // anyway. Reading them one at a time is much slower.
-
- // Write the jump back to address 1.
- scans_add_write_jump(scans, 1, false);
- for (int reg = 1; reg < 32; reg++) {
- if (reg == S0 || reg == S1) {
- continue;
- }
-
- // Write store instruction.
- scans_add_write_store(scans, 0, reg, SLOT0, true);
-
- // Read value.
- scans_add_read(scans, SLOT0, false);
- }
-
- // Write store of s0 at index 1.
- scans_add_write_store(scans, 1, S0, SLOT0, false);
- // Write jump at index 2.
- scans_add_write_jump(scans, 2, false);
-
- // Read S1 from debug RAM
- scans_add_write_load(scans, 0, S0, SLOT_LAST, true);
- // Read value.
- scans_add_read(scans, SLOT0, false);
-
- // Read S0 from dscratch
- unsigned int csr[] = {CSR_DSCRATCH, CSR_DPC, CSR_DCSR};
- for (unsigned int i = 0; i < DIM(csr); i++) {
- scans_add_write32(scans, 0, csrr(S0, csr[i]), true);
- scans_add_read(scans, SLOT0, false);
- }
-
- // Final read to get the last value out.
- scans_add_read32(scans, 4, false);
-
- int retval = scans_execute(scans);
- if (retval != ERROR_OK) {
- LOG_ERROR("JTAG execute failed: %d", retval);
- goto error;
- }
-
- unsigned int dbus_busy = 0;
- unsigned int interrupt_set = 0;
- unsigned result = 0;
- uint64_t value = 0;
- reg_cache_set(target, 0, 0);
- // The first scan result is the result from something old we don't care
- // about.
- for (unsigned int i = 1; i < scans->next_scan && dbus_busy == 0; i++) {
- dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
- DBUS_OP_SIZE);
- uint64_t data = scans_get_u64(scans, i, DBUS_DATA_START, DBUS_DATA_SIZE);
- uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
- info->addrbits);
- switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug access failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
- }
- if (data & DMCONTROL_INTERRUPT) {
- interrupt_set++;
- break;
- }
- if (address == 4 || address == 5) {
- unsigned int reg;
- switch (result) {
- case 0: reg = 1; break;
- case 1: reg = 2; break;
- case 2: reg = 3; break;
- case 3: reg = 4; break;
- case 4: reg = 5; break;
- case 5: reg = 6; break;
- case 6: reg = 7; break;
- // S0
- // S1
- case 7: reg = 10; break;
- case 8: reg = 11; break;
- case 9: reg = 12; break;
- case 10: reg = 13; break;
- case 11: reg = 14; break;
- case 12: reg = 15; break;
- case 13: reg = 16; break;
- case 14: reg = 17; break;
- case 15: reg = 18; break;
- case 16: reg = 19; break;
- case 17: reg = 20; break;
- case 18: reg = 21; break;
- case 19: reg = 22; break;
- case 20: reg = 23; break;
- case 21: reg = 24; break;
- case 22: reg = 25; break;
- case 23: reg = 26; break;
- case 24: reg = 27; break;
- case 25: reg = 28; break;
- case 26: reg = 29; break;
- case 27: reg = 30; break;
- case 28: reg = 31; break;
- case 29: reg = S1; break;
- case 30: reg = S0; break;
- case 31: reg = CSR_DPC; break;
- case 32: reg = CSR_DCSR; break;
- default:
- assert(0);
- }
- if (info->xlen == 32) {
- reg_cache_set(target, reg, data & 0xffffffff);
- result++;
- } else if (info->xlen == 64) {
- if (address == 4) {
- value = data & 0xffffffff;
- } else if (address == 5) {
- reg_cache_set(target, reg, ((data & 0xffffffff) << 32) | value);
- value = 0;
- result++;
- }
- }
- }
- }
-
- if (dbus_busy) {
- increase_dbus_busy_delay(target);
- return RE_AGAIN;
- }
- if (interrupt_set) {
- increase_interrupt_high_delay(target);
- return RE_AGAIN;
- }
-
- // TODO: get rid of those 2 variables and talk to the cache directly.
- info->dpc = reg_cache_get(target, CSR_DPC);
- info->dcsr = reg_cache_get(target, CSR_DCSR);
- scans = scans_delete(scans);
-
- cache_invalidate(target);
-
- return RE_OK;
-
-error:
- scans = scans_delete(scans);
- return RE_FAIL;
-}
-
-static int handle_halt(struct target *target, bool announce)
-{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- target->state = TARGET_HALTED;
-
- riscv_error_t re;
- do {
- re = handle_halt_routine(target);
- } while (re == RE_AGAIN);
- if (re != RE_OK) {
- LOG_ERROR("handle_halt_routine failed");
- return ERROR_FAIL;
- }
-
- int cause = get_field(info->dcsr, DCSR_CAUSE);
- switch (cause) {
- case DCSR_CAUSE_SWBP:
- target->debug_reason = DBG_REASON_BREAKPOINT;
- break;
- case DCSR_CAUSE_HWBP:
- target->debug_reason = DBG_REASON_WPTANDBKPT;
- // If we halted because of a data trigger, gdb doesn't know to do
- // the disable-breakpoints-step-enable-breakpoints dance.
- info->need_strict_step = true;
- break;
- case DCSR_CAUSE_DEBUGINT:
- target->debug_reason = DBG_REASON_DBGRQ;
- break;
- case DCSR_CAUSE_STEP:
- target->debug_reason = DBG_REASON_SINGLESTEP;
- break;
- case DCSR_CAUSE_HALT:
- default:
- LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
- cause, info->dcsr);
- }
-
- if (info->never_halted) {
- info->never_halted = false;
-
- // Disable any hardware triggers that have dmode set. We can't have set
- // them ourselves. Maybe they're left over from some killed debug
- // session.
- // Count the number of triggers while we're at it.
-
- int result = maybe_read_tselect(target);
- if (result != ERROR_OK)
- return result;
- for (info->trigger_count = 0; info->trigger_count < MAX_HWBPS; info->trigger_count++) {
- write_csr(target, CSR_TSELECT, info->trigger_count);
- uint64_t tselect_rb;
- read_csr(target, &tselect_rb, CSR_TSELECT);
- if (info->trigger_count != tselect_rb)
- break;
- uint64_t tdata1;
- read_csr(target, &tdata1, CSR_TDATA1);
- if ((tdata1 & MCONTROL_DMODE(info->xlen)) &&
- (tdata1 & (MCONTROL_EXECUTE | MCONTROL_STORE | MCONTROL_LOAD))) {
- write_csr(target, CSR_TDATA1, 0);
- }
- }
- }
-
- if (announce) {
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- }
-
- const char *cause_string[] = {
- "none",
- "software breakpoint",
- "hardware trigger",
- "debug interrupt",
- "step",
- "halt"
- };
- // This is logged to the user so that gdb will show it when a user types
- // 'monitor reset init'. At that time gdb appears to have the pc cached
- // still so if a user manually inspects the pc it will still have the old
- // value.
- LOG_USER("halted at 0x%" PRIx64 " due to %s", info->dpc, cause_string[cause]);
-
- return ERROR_OK;
-}
-
-static int poll_target(struct target *target, bool announce)
-{
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- // Inhibit debug logging during poll(), which isn't usually interesting and
- // just fills up the screen/logs with clutter.
- int old_debug_level = debug_level;
- if (debug_level >= LOG_LVL_DEBUG) {
- debug_level = LOG_LVL_INFO;
- }
- bits_t bits = read_bits(target);
- debug_level = old_debug_level;
-
- if (bits.haltnot && bits.interrupt) {
- target->state = TARGET_DEBUG_RUNNING;
- LOG_DEBUG("debug running");
- } else if (bits.haltnot && !bits.interrupt) {
- if (target->state != TARGET_HALTED) {
- return handle_halt(target, announce);
- }
- } else if (!bits.haltnot && bits.interrupt) {
- // Target is halting. There is no state for that, so don't change anything.
- LOG_DEBUG("halting");
- } else if (!bits.haltnot && !bits.interrupt) {
- target->state = TARGET_RUNNING;
- }
-
- return ERROR_OK;
+ return tt->examine(target);
}
static int riscv_poll(struct target *target)
{
- return poll_target(target, true);
+ struct target_type *tt = get_target_type(target);
+ return tt->poll(target);
}
static int riscv_resume(struct target *target, int current, uint32_t address,
int handle_breakpoints, int debug_execution)
{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
-
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- if (!current) {
- if (info->xlen > 32) {
- LOG_WARNING("Asked to resume at 32-bit PC on %d-bit target.",
- info->xlen);
- }
- int result = register_write(target, REG_PC, address);
- if (result != ERROR_OK)
- return result;
- }
-
- if (info->need_strict_step || handle_breakpoints) {
- int result = strict_step(target, false);
- if (result != ERROR_OK)
- return result;
- }
-
- return resume(target, debug_execution, false);
+ struct target_type *tt = get_target_type(target);
+ return tt->resume(target, current, address, handle_breakpoints,
+ debug_execution);
}
static int riscv_assert_reset(struct target *target)
{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- // TODO: Maybe what I implemented here is more like soft_reset_halt()?
-
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- // The only assumption we can make is that the TAP was reset.
- if (wait_for_debugint_clear(target, true) != ERROR_OK) {
- LOG_ERROR("Debug interrupt didn't clear.");
- return ERROR_FAIL;
- }
-
- // Not sure what we should do when there are multiple cores.
- // Here just reset the single hart we're talking to.
- info->dcsr |= DCSR_EBREAKM | DCSR_EBREAKH | DCSR_EBREAKS |
- DCSR_EBREAKU | DCSR_HALT;
- if (target->reset_halt) {
- info->dcsr |= DCSR_NDRESET;
- } else {
- info->dcsr |= DCSR_FULLRESET;
- }
- dram_write32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16), false);
- dram_write32(target, 1, csrw(S0, CSR_DCSR), false);
- // We shouldn't actually need the jump because a reset should happen.
- dram_write_jump(target, 2, false);
- dram_write32(target, 4, info->dcsr, true);
- cache_invalidate(target);
-
- target->state = TARGET_RESET;
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->assert_reset(target);
}
static int riscv_deassert_reset(struct target *target)
{
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
- if (target->reset_halt) {
- return wait_for_state(target, TARGET_HALTED);
- } else {
- return wait_for_state(target, TARGET_RUNNING);
- }
+ struct target_type *tt = get_target_type(target);
+ return tt->deassert_reset(target);
}
static int riscv_read_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
- switch (size) {
- case 1:
- cache_set32(target, 1, lb(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- case 2:
- cache_set32(target, 1, lh(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- case 4:
- cache_set32(target, 1, lw(S1, S0, 0));
- cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
- break;
- default:
- LOG_ERROR("Unsupported size: %d", size);
- return ERROR_FAIL;
- }
- cache_set_jump(target, 3);
- cache_write(target, CACHE_NO_READ, false);
-
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- const int max_batch_size = 256;
- scans_t *scans = scans_new(target, max_batch_size);
-
- uint32_t result_value = 0x777;
- uint32_t i = 0;
- while (i < count + 3) {
- unsigned int batch_size = MIN(count + 3 - i, max_batch_size);
- scans_reset(scans);
-
- for (unsigned int j = 0; j < batch_size; j++) {
- if (i + j == count) {
- // Just insert a read so we can scan out the last value.
- scans_add_read32(scans, 4, false);
- } else if (i + j >= count + 1) {
- // And check for errors.
- scans_add_read32(scans, info->dramsize-1, false);
- } else {
- // Write the next address and set interrupt.
- uint32_t offset = size * (i + j);
- scans_add_write32(scans, 4, address + offset, true);
- }
- }
-
- int retval = scans_execute(scans);
- if (retval != ERROR_OK) {
- LOG_ERROR("JTAG execute failed: %d", retval);
- goto error;
- }
-
- int dbus_busy = 0;
- int execute_busy = 0;
- for (unsigned int j = 0; j < batch_size; j++) {
- dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
- DBUS_OP_SIZE);
- switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
- }
- uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
- DBUS_DATA_SIZE);
- if (data & DMCONTROL_INTERRUPT) {
- execute_busy++;
- }
- if (i + j == count + 2) {
- result_value = data;
- } else if (i + j > 1) {
- uint32_t offset = size * (i + j - 2);
- switch (size) {
- case 1:
- buffer[offset] = data;
- break;
- case 2:
- buffer[offset] = data;
- buffer[offset+1] = data >> 8;
- break;
- case 4:
- buffer[offset] = data;
- buffer[offset+1] = data >> 8;
- buffer[offset+2] = data >> 16;
- buffer[offset+3] = data >> 24;
- break;
- }
- }
- LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
- }
- if (dbus_busy) {
- increase_dbus_busy_delay(target);
- }
- if (execute_busy) {
- increase_interrupt_high_delay(target);
- }
- if (dbus_busy || execute_busy) {
- wait_for_debugint_clear(target, false);
-
- // Retry.
- LOG_INFO("Retrying memory read starting from 0x%x with more delays",
- address + size * i);
- } else {
- i += batch_size;
- }
- }
-
- if (result_value != 0) {
- LOG_USER("Core got an exception (0x%x) while reading from 0x%x",
- result_value, address + size * (count-1));
- if (count > 1) {
- LOG_USER("(It may have failed between 0x%x and 0x%x as well, but we "
- "didn't check then.)",
- address, address + size * (count-2) + size - 1);
- }
- goto error;
- }
-
- scans_delete(scans);
- cache_clean(target);
- return ERROR_OK;
-
-error:
- scans_delete(scans);
- cache_clean(target);
- return ERROR_FAIL;
-}
-
-static int setup_write_memory(struct target *target, uint32_t size)
-{
- switch (size) {
- case 1:
- cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sb(S0, T0, 0));
- break;
- case 2:
- cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sh(S0, T0, 0));
- break;
- case 4:
- cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
- cache_set32(target, 1, sw(S0, T0, 0));
- break;
- default:
- LOG_ERROR("Unsupported size: %d", size);
- return ERROR_FAIL;
- }
- cache_set32(target, 2, addi(T0, T0, size));
- cache_set_jump(target, 3);
- cache_write(target, 4, false);
-
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->read_memory(target, address, size, count, buffer);
}
static int riscv_write_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, const uint8_t *buffer)
{
- riscv_info_t *info = (riscv_info_t *) target->arch_info;
- jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
-
- // Set up the address.
- cache_set_store(target, 0, T0, SLOT1);
- cache_set_load(target, 1, T0, SLOT0);
- cache_set_jump(target, 2);
- cache_set(target, SLOT0, address);
- if (cache_write(target, 5, true) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- uint64_t t0 = cache_get(target, SLOT1);
- LOG_DEBUG("t0 is 0x%" PRIx64, t0);
-
- if (setup_write_memory(target, size) != ERROR_OK) {
- return ERROR_FAIL;
- }
-
- const int max_batch_size = 256;
- scans_t *scans = scans_new(target, max_batch_size);
-
- uint32_t result_value = 0x777;
- uint32_t i = 0;
- while (i < count + 2) {
- unsigned int batch_size = MIN(count + 2 - i, max_batch_size);
- scans_reset(scans);
-
- for (unsigned int j = 0; j < batch_size; j++) {
- if (i + j >= count) {
- // Check for an exception.
- scans_add_read32(scans, info->dramsize-1, false);
- } else {
- // Write the next value and set interrupt.
- uint32_t value;
- uint32_t offset = size * (i + j);
- switch (size) {
- case 1:
- value = buffer[offset];
- break;
- case 2:
- value = buffer[offset] |
- (buffer[offset+1] << 8);
- break;
- case 4:
- value = buffer[offset] |
- ((uint32_t) buffer[offset+1] << 8) |
- ((uint32_t) buffer[offset+2] << 16) |
- ((uint32_t) buffer[offset+3] << 24);
- break;
- default:
- goto error;
- }
-
- scans_add_write32(scans, 4, value, true);
- }
- }
-
- int retval = scans_execute(scans);
- if (retval != ERROR_OK) {
- LOG_ERROR("JTAG execute failed: %d", retval);
- goto error;
- }
-
- int dbus_busy = 0;
- int execute_busy = 0;
- for (unsigned int j = 0; j < batch_size; j++) {
- dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
- DBUS_OP_SIZE);
- switch (status) {
- case DBUS_STATUS_SUCCESS:
- break;
- case DBUS_STATUS_FAILED:
- LOG_ERROR("Debug RAM write failed. Hardware error?");
- goto error;
- case DBUS_STATUS_BUSY:
- dbus_busy++;
- break;
- default:
- LOG_ERROR("Got invalid bus access status: %d", status);
- return ERROR_FAIL;
- }
- int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
- if (interrupt) {
- execute_busy++;
- }
- if (i + j == count + 1) {
- result_value = scans_get_u32(scans, j, DBUS_DATA_START, 32);
- }
- }
- if (dbus_busy) {
- increase_dbus_busy_delay(target);
- }
- if (execute_busy) {
- increase_interrupt_high_delay(target);
- }
- if (dbus_busy || execute_busy) {
- wait_for_debugint_clear(target, false);
-
- // Retry.
- // Set t0 back to what it should have been at the beginning of this
- // batch.
- LOG_INFO("Retrying memory write starting from 0x%x with more delays",
- address + size * i);
-
- cache_clean(target);
-
- if (write_gpr(target, T0, address + size * i) != ERROR_OK) {
- goto error;
- }
-
- if (setup_write_memory(target, size) != ERROR_OK) {
- goto error;
- }
- } else {
- i += batch_size;
- }
- }
-
- if (result_value != 0) {
- LOG_ERROR("Core got an exception (0x%x) while writing to 0x%x",
- result_value, address + size * (count-1));
- if (count > 1) {
- LOG_ERROR("(It may have failed between 0x%x and 0x%x as well, but we "
- "didn't check then.)",
- address, address + size * (count-2) + size - 1);
- }
- goto error;
- }
-
- cache_clean(target);
- return register_write(target, T0, t0);
-
-error:
- scans_delete(scans);
- cache_clean(target);
- return ERROR_FAIL;
+ struct target_type *tt = get_target_type(target);
+ return tt->write_memory(target, address, size, count, buffer);
}
static int riscv_get_gdb_reg_list(struct target *target,
@@ -2640,7 +430,8 @@ static int riscv_get_gdb_reg_list(struct target *target,
static int riscv_arch_state(struct target *target)
{
- return ERROR_OK;
+ struct target_type *tt = get_target_type(target);
+ return tt->arch_state(target);
}
// Algorithm must end with a software breakpoint instruction.
@@ -2662,10 +453,11 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
}
/// Save registers
- if (register_get(&target->reg_cache->reg_list[REG_PC]) != ERROR_OK) {
+ struct reg *reg_pc = register_get_by_name(target->reg_cache, "pc", 1);
+ if (!reg_pc || reg_pc->type->get(reg_pc) != ERROR_OK) {
return ERROR_FAIL;
}
- uint64_t saved_pc = reg_cache_get(target, REG_PC);
+ uint64_t saved_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
uint64_t saved_regs[32];
for (int i = 0; i < num_reg_params; i++) {
@@ -2687,11 +479,11 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
return ERROR_FAIL;
}
- if (register_get(r) != ERROR_OK) {
+ if (r->type->get(r) != ERROR_OK) {
return ERROR_FAIL;
}
- saved_regs[r->number] = buf_get_u64(r->value, 0, info->xlen);
- if (register_set(r, reg_params[i].value) != ERROR_OK) {
+ saved_regs[r->number] = buf_get_u64(r->value, 0, r->size);
+ if (r->type->set(r, reg_params[i].value) != ERROR_OK) {
return ERROR_FAIL;
}
}
@@ -2702,12 +494,17 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
uint8_t mstatus_bytes[8];
LOG_DEBUG("Disabling Interrupts");
- register_get(&target->reg_cache->reg_list[REG_MSTATUS]);
- current_mstatus = buf_get_u64(target->reg_cache->reg_list[REG_MSTATUS].value, 0, info->xlen);
+ char mstatus_name[20];
+ sprintf(mstatus_name, "csr%d", CSR_MSTATUS);
+ struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
+ mstatus_name, 1);
+ reg_mstatus->type->get(reg_mstatus);
+ current_mstatus = buf_get_u64(reg_mstatus->value, 0, reg_mstatus->size);
uint64_t ie_mask = MSTATUS_MIE | MSTATUS_HIE | MSTATUS_SIE | MSTATUS_UIE;
- buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus, ie_mask, 0));
+ buf_set_u64(mstatus_bytes, 0, info->xlen, set_field(current_mstatus,
+ ie_mask, 0));
- register_set(&target->reg_cache->reg_list[REG_MSTATUS], mstatus_bytes);
+ reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
/// Run algorithm
LOG_DEBUG("resume at 0x%x", entry_point);
@@ -2732,10 +529,10 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
}
}
- if (register_get(&target->reg_cache->reg_list[REG_PC]) != ERROR_OK) {
+ if (reg_pc->type->get(reg_pc) != ERROR_OK) {
return ERROR_FAIL;
}
- uint64_t final_pc = reg_cache_get(target, REG_PC);
+ uint64_t final_pc = buf_get_u64(reg_pc->value, 0, reg_pc->size);
if (final_pc != exit_point) {
LOG_ERROR("PC ended up at 0x%" PRIx64 " instead of 0x%" PRIx32,
final_pc, exit_point);
@@ -2745,12 +542,12 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
// Restore Interrupts
LOG_DEBUG("Restoring Interrupts");
buf_set_u64(mstatus_bytes, 0, info->xlen, current_mstatus);
- register_set(&target->reg_cache->reg_list[REG_MSTATUS], mstatus_bytes);
+ reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
/// Restore registers
uint8_t buf[8];
buf_set_u64(buf, 0, info->xlen, saved_pc);
- if (register_set(&target->reg_cache->reg_list[REG_PC], buf) != ERROR_OK) {
+ if (reg_pc->type->set(reg_pc, buf) != ERROR_OK) {
return ERROR_FAIL;
}
@@ -2758,7 +555,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
LOG_DEBUG("restore %s", reg_params[i].reg_name);
struct reg *r = register_get_by_name(target->reg_cache, reg_params[i].reg_name, 0);
buf_set_u64(buf, 0, info->xlen, saved_regs[r->number]);
- if (register_set(r, buf) != ERROR_OK) {
+ if (r->type->set(r, buf) != ERROR_OK) {
return ERROR_FAIL;
}
}
@@ -2770,12 +567,12 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
memory. Not yet implemented.
*/
-int riscv_checksum_memory(struct target *target,
+static int riscv_checksum_memory(struct target *target,
uint32_t address, uint32_t count,
- uint32_t* checksum) {
+ uint32_t* checksum)
+{
*checksum = 0xFFFFFFFF;
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* Should run code on the target to check whether a memory
@@ -2783,14 +580,14 @@ block holds all-ones (because this is generally called on
NOR flash which is 1 when "blank")
Not yet implemented.
*/
-
int riscv_blank_check_memory(struct target * target,
uint32_t address,
uint32_t count,
- uint32_t * blank) {
+ uint32_t * blank)
+{
*blank = 0;
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
struct target_type riscv_target =
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
new file mode 100644
index 0000000..3439a56
--- /dev/null
+++ b/src/target/riscv/riscv.h
@@ -0,0 +1,62 @@
+#ifndef RISCV_H
+#define RISCV_H
+
+#include "opcodes.h"
+
+extern struct target_type riscv011_target;
+extern struct target_type riscv013_target;
+
+/*
+ * Definitions shared by code supporting all RISC-V versions.
+ */
+
+typedef struct {
+ unsigned dtm_version;
+ struct command_context *cmd_ctx;
+ void *version_specific;
+ /* Width of a GPR (and many other things) in bits. */
+ uint8_t xlen;
+} riscv_info_t;
+
+extern uint8_t ir_dtmcontrol[1];
+extern struct scan_field select_dtmcontrol;
+extern uint8_t ir_dbus[1];
+extern struct scan_field select_dbus;
+extern uint8_t ir_idcode[1];
+extern struct scan_field select_idcode;
+
+/*** Version-independent functions that we don't want in the main address space. ***/
+
+static uint32_t load(const struct target *target, unsigned int rd,
+ unsigned int base, uint16_t offset)
+{
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ switch (info->xlen) {
+ case 32:
+ return lw(rd, base, offset);
+ case 64:
+ return ld(rd, base, offset);
+ }
+ assert(0);
+}
+
+static uint32_t store(const struct target *target, unsigned int src,
+ unsigned int base, uint16_t offset)
+{
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ switch (info->xlen) {
+ case 32:
+ return sw(src, base, offset);
+ case 64:
+ return sd(src, base, offset);
+ }
+ assert(0);
+}
+
+static unsigned xlen(const struct target *target)
+{
+ riscv_info_t *info = (riscv_info_t *) target->arch_info;
+ return info->xlen;
+}
+
+#endif
generated by cgit v1.1 at 2024-11-16 07:06:04 +0000