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| author | Tim Newsome <tim@sifive.com> | 2018-11-05 11:48:52 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-11-05 11:48:52 -0800 |
| commit | ca1a1f8db73559a98c878f31952ca850e6d1cf73 (patch) | |
| tree | 5adb84763d05216089f898dbd53fdf5fb97a97a2 /.travis.yml | |
| parent | 60368dd62e29fe728e9987010bc9c8b0b5815af3 (diff) | |
| download | riscv-openocd-ca1a1f8db73559a98c878f31952ca850e6d1cf73.zip riscv-openocd-ca1a1f8db73559a98c878f31952ca850e6d1cf73.tar.gz riscv-openocd-ca1a1f8db73559a98c878f31952ca850e6d1cf73.tar.bz2 | |
Complete single step before returning. (#319)
This fixes the following error, that has been reported occasionally:
Error: 34072 2712 riscv-011.c:1175 reg_cache_get(): Register cache entry for 0 is invalid!
openocd: ../src/target/riscv/riscv-011.c:1176: reg_cache_get: Assertion `r->valid' failed.
The problem was that we'd tell the target to step, and then gdb (which
assumed the target halted already) asked to read a register before the
target had actually halted. With this fix the target is actually halted,
and everything works.
Change-Id: Icfcef456f3cec4bb352fb90186f5bbabb00a5ff8
Diffstat (limited to '.travis.yml')
0 files changed, 0 insertions, 0 deletions