index
:
riscv-openocd.git
FE_402_fix
__archive__
add_macos_build
autoconf
bscan_optimization
bscan_tunnel
buf_sget
build32
busy
compliance_dev
debug-log-reg-failure
deinit
dmi_read
dmstatus_version
dsp5680_build
eclipse_memory_read
eclipse_multicore_fix
examine_command
examine_unavailable_harts
examine_unavailable_harts_backup
examine_unavailable_harts_rebase
examine_unavailable_harts_squash
fence_i_fix_for_release
fix-halt-reason-after-singlestep
fix_macbuild
gd32vf103
gdb_next_port
gitignore-build
global
halt_examine
haltreq
hypervisor_translate
jlink
log_output
macbuild
macro
manual_hwbp
master
mem64
mpsse_flush
multicore
new_bscan_approach
newprogram
nohartstatus
old_fixes_and_eclipse_memory_read
old_triggers
print_port
race
rbb_cleanup
regcache
regression_test_janmat_experim
release
remove-slot_t-from-riscv-013
reset_test
reverse-resume-order
riscv
riscv-batch-cleanup
riscv-compliance
riscv-compliance-dev
s2_increment
sba_tests
set_group
static
travis-nop
update_defines
us_xds110
vector2
winbuild
wip
Unnamed repository; edit this file 'description' to name the repository.
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Commit message
Author
Age
examine_unavailable_harts
Handling harts becoming available when halted
cgsfv
4 months
examine_unavailable_harts_backup
Handle unavailability when deasserting reset
cgsfv
4 months
examine_unavailable_harts_rebase
Improved handling of unavailable cores
cgsfv
4 months
examine_unavailable_harts_squash
Improved handling of unavailable harts
cgsfv
4 months
hypervisor_translate
target/riscv: Support VS-stage and G-stage address translation.
Tim Newsome
16 months
remove-slot_t-from-riscv-013
riscv-013: Remove unused typedef slot_t
Jan Matyas
3 months
reset_test
DMI read before asserting ndmreset/haltreq.
Tim Newsome
11 months
riscv
Merge pull request #1114 from en-sc/en-sc/dup-dtmcontrol
Evgeniy Naydanov
10 days
riscv-batch-cleanup
Fixes of review findings
Jan Matyas
6 months
us_xds110
jtag/drivers/xds110: Fix compiler warning.
Tim Newsome
13 months
[...]
Tag
Download
Author
Age
latest
riscv-openocd-latest.zip
riscv-openocd-latest.tar.gz
riscv-openocd-latest.tar.bz2
Evgeniy Naydanov
10 days
openocd64-ad4c3e1
riscv-openocd-openocd64-ad4c3e1.zip
riscv-openocd-openocd64-ad4c3e1.tar.gz
riscv-openocd-openocd64-ad4c3e1.tar.bz2
Tim Newsome
17 months
openocd64-8b80fe1
riscv-openocd-openocd64-8b80fe1.zip
riscv-openocd-openocd64-8b80fe1.tar.gz
riscv-openocd-openocd64-8b80fe1.tar.bz2
Tim Newsome
17 months
openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461
riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.zip
riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.tar.gz
riscv-openocd-openocd64-41b9c69e92d9660cb2eff508f3bc8218a3b3e461.tar.bz2
Tim Newsome
17 months
openocd64-d486b21
riscv-openocd-openocd64-d486b21.zip
riscv-openocd-openocd64-d486b21.tar.gz
riscv-openocd-openocd64-d486b21.tar.bz2
Tim Newsome
17 months
v2018.12.0
riscv-openocd-2018.12.0.zip
riscv-openocd-2018.12.0.tar.gz
riscv-openocd-2018.12.0.tar.bz2
Tim Newsome
6 years
v20181030
riscv-openocd-20181030.zip
riscv-openocd-20181030.tar.gz
riscv-openocd-20181030.tar.bz2
Tim Newsome
6 years
v20180928
riscv-openocd-20180928.zip
riscv-openocd-20180928.tar.gz
riscv-openocd-20180928.tar.bz2
cgsfv
6 years
v20180629
riscv-openocd-20180629.zip
riscv-openocd-20180629.tar.gz
riscv-openocd-20180629.tar.bz2
Palmer Dabbelt
6 years
v20171231
riscv-openocd-20171231.zip
riscv-openocd-20171231.tar.gz
riscv-openocd-20171231.tar.bz2
Palmer Dabbelt
7 years
[...]
Age
Commit message
Author
Files
Lines
10 days
Merge pull request #1114 from en-sc/en-sc/dup-dtmcontrol
HEAD
latest
riscv
Evgeniy Naydanov
4
-81
/
+19
10 days
Merge pull request #1101 from en-sc/en-sc/ref-reg-examine
Evgeniy Naydanov
7
-122
/
+239
12 days
target/riscv: remove duplicate `dtmcontrol_scan()`
Evgeniy Naydanov
4
-81
/
+19
12 days
target/riscv: reg cache entry is initialized before access
Evgeniy Naydanov
7
-122
/
+239
2024-08-08
Merge pull request #1104 from TommyMurphyTM1234/fix-include-guards
Evgeniy Naydanov
12
-26
/
+35
2024-07-18
Merge pull request #1100 from en-sc/en-sc/single-as-batch
Evgeniy Naydanov
5
-272
/
+74
2024-07-16
target/riscv: single DMI accesses via batch
Evgeniy Naydanov
5
-272
/
+74
2024-07-12
Merge pull request #1099 from en-sc/en-sc/sb-addr-batch
Evgeniy Naydanov
1
-38
/
+37
2024-07-10
target/riscv: write SB address using batch
Evgeniy Naydanov
1
-38
/
+37
2024-07-09
Merge pull request #1096 from en-sc/en-sc/run-batch-busy
Evgeniy Naydanov
1
-3
/
+7
[...]