| Branch | Commit message | Author | Age | |
|---|---|---|---|---|
| asciidoc_artifact | Pre commit fixes | IIITM-Jay | 3 months | |
| c_modularized | Refactored and modularized C Artifact Generation | IIITM-Jay | 3 months | |
| confprec | Add vsetprec instruction | Quan Nguyen | 11 years | |
| debug | Update the debug CSR definitions for the proposed 0.13 debug spec | Palmer Dabbelt | 8 years | |
| incoresemi-migration-to-new-format | Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv... | Andrew Waterman | 3 years | |
| llvm-encodings | WIP: auto-generate llvm encoding file | Colin Schmidt | 9 years | |
| master | Add encodings for Zvqdotq instrutions (#337) | Andrew Waterman | 7 days | |
| mvp | Add vf[ls]seg(|st)h and friends | Quan Nguyen | 11 years | |
| riscv-bitmanip | Remove subu.w | Andrew Waterman | 4 years | |
| rnmi | Add RNMI CSRs and instruction | Andrew Waterman | 3 years | |
| rvv | Fix config imms | Colin Schmidt | 6 years | |
| v | CSRRx is called Zicsr | Andrew Waterman | 6 years | |
| vadc | Update encoding of vadc and friends | Andrew Waterman | 5 years | |
| wfmi | Add wfmi instruction | Andrew Waterman | 4 years | |
| zfh | Add tentative RV32Zfh encoding | Andrew Waterman | 5 years | |
 |
index : riscv-opcodes.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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