riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
asciidoc_artifact	Pre commit fixes	IIITM-Jay	13 months
c-ret	Add c.ret pseudo	Andrew Waterman	7 weeks
c_modularized	Refactored and modularized C Artifact Generation	IIITM-Jay	13 months
confprec	Add vsetprec instruction	Quan Nguyen	12 years
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	9 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	4 years
llvm-encodings	WIP: auto-generate llvm encoding file	Colin Schmidt	9 years
master	Change immediate type of select vector-immediate instructions to zimm5 (#393)	robinali-codasip	4 weeks
mvp	Add vf[ls]seg(\|st)h and friends	Quan Nguyen	12 years
riscv-bitmanip	Remove subu.w	Andrew Waterman	5 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	4 years
rvv	Fix config imms	Colin Schmidt	7 years
v	CSRRx is called Zicsr	Andrew Waterman	7 years
vadc	Update encoding of vadc and friends	Andrew Waterman	6 years
wfmi	Add wfmi instruction	Andrew Waterman	5 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	6 years