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| author | Andrew Waterman <andrew@sifive.com> | 2025-11-12 01:03:51 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2025-11-12 01:45:08 -0800 |
| commit | 28a3c8bc7ded6e3f8c734319e18e4425a0e578e1 (patch) | |
| tree | d0ee26eb704f5c28ecc966e812cecc9fe27aa5c4 | |
| parent | f1aa1dea6814035fa2cd3ee4603dc4ac1c644069 (diff) | |
| download | riscv-opcodes-c-ret.zip riscv-opcodes-c-ret.tar.gz riscv-opcodes-c-ret.tar.bz2 | |
Add c.ret pseudoc-ret
Needed by Spike
| -rw-r--r-- | extensions/rv_c | 2 | ||||
| -rw-r--r-- | src/riscv_opcodes/constants.py | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/extensions/rv_c b/extensions/rv_c index 6fda454..fbccca3 100644 --- a/extensions/rv_c +++ b/extensions/rv_c @@ -26,3 +26,5 @@ c.ebreak 1..0=2 15..13=4 12=1 11..2=0 c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 c.add rd_rs1_n0 c_rs2_n0 1..0=2 15..13=4 12=1 c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 + +$pseudo_op rv_c::c.jr c.ret 11..7=1 1..0=2 15..13=4 12=0 6..2=0 diff --git a/src/riscv_opcodes/constants.py b/src/riscv_opcodes/constants.py index 49447a7..62381ae 100644 --- a/src/riscv_opcodes/constants.py +++ b/src/riscv_opcodes/constants.py @@ -204,6 +204,7 @@ emitted_pseudo_ops = [ "srai_rv32", "srli_rv32", "umax32", + "c_ret", "c_mop_1", "c_sspush_x1", "c_mop_3", |