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add `_n0' on `rd` for `c.li`, `c.mv`, `c.add`, and `c.lqsp`.
Signed-off-by: Hiroo HAYASHI <24754036+hirooih@users.noreply.github.com>
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store-releasee
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confusion hopefully
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the load-acquire byte (so `lb.aq` and `lb.aqrl`), I'm not sure that will work but it passes the tests here.
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* add mop.r.N and mop.rr.N pseudo-inst
* add c.mop.N pseudo-inst
* add arg_lut entries and emitted pseudoops for Zimop/Zcmop
* add pseudoinsts for Zimop
* add pseudoinsts for Zcmop
* update zcmop mnemonics
* update zcmop mnemonics
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C.ADDIW cannot have an rd of 0
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The code point of rd=0 in C.ADDIW is restricted.
Fix formatting while in these files.
Signed-off-by: Charlie Jenkins <charlie@rivosinc.com>
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Add encodings for all instructions in the Zvk extensions:
- Zvbb, Vector Bit-manipulation instructions used in Cryptography,
- Zvbc, Vector Carryless Multiplication
- Zvkg, Vector GCM/GMAC instruction for Cryptography,
- Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single
Round),
- Zvknha, Zvknhb, NIST Suite: Vector SHA-2,
- Zvksed, ShangMi Suite: SM4 Block Cipher Instructions
- Zvkssh, ShangMi Suite: SM3 Hash Function Instructions
Add two "shorthand" extensions:
- Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh
- Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh
Three new fields are listed in constants.py:
- 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh),
and 5-bit shift constant (vwsll.vi in Zvbb)
- 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount
in vror.vi.
The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the
P opcode space. Some encodings conflict with proposed instructions
in the P extension (packed SIMD). Zvk and P are exclusive of each
other, no implementation will implement both. Conflicting P instructions
are marked as pseudo of the Zvk instructions.
The encodings match the current documentation of the specification
at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>,
at Version v0.9.1, 25 April, 2023 (Freeze Candidate).
Co-authored-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Zfa adds 'missing' floating-point functionality:
- fli.[hsdq]: floating-point load-immediate
- fminm/fmaxm.[hsdq]: IEEE 754-2019 minimum and maximum
- fround(nx)?.[hsdq]: IEEE 754-2019 roundToIntegral(Exact)?
- fcvtmod.w.d: ECMAScript modular float->integer conversion
- move instructions for XLEN < FLEN
- comparisons that support quiet NaN inputs
This adds a surprisingly large number of files, as the instructions
added with Zfa depend on context (e.g., .h-variants become available
only if Zfh is present).
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Forgot to add this as part of #168.
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GREV instruction no longer exist in the zbpbo specified by [v0.9.11 spec](https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc#51-zbpbo)
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* Move Zawrs to ratified folder
* Move Zawrs to ratified folder
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This reverts commit 24cba79065aa975ad91e92c5d59f2e1dafa5ab26.
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This reverts commit 3485bbcda5509615e4d18708722d67871efb7eaf.
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This reverts commit 6b5a0648ab6b99507aef3c902afbcd3cd9d90353.
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This reverts commit 9b0eddd52b9e3c1fbd1dab56ecbaa88747254a2a.
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This reverts commit 2cf6da8f9a370ee5c0012d4ae4f403c3d920d1e8.
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This reverts commit 115e4237407e8c02b945dfb12c086ee57200dd55.
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Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI,
and SRAI. Thus, downstream tooling that relies on these to connote the
RV64 variants of these instructions is semantically affected.
Fix by reverting SLLI etc. to being the RV64 variants.
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This will reduce the chance that people pick the wrong shamt width.
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pack instruction should be imported from zbe -- instead of zbp.
Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
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Removing import of csrrs and crrci as the instruction's pseudo opcode for is already included.
Signed-off-by: Babu P S <11073327+eflaner@users.noreply.github.com>
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* Correction of riscv-p-spec opcodes
- Reorganized 'p' into sub-extensions zpn, zpfs & zbpbo
- Some instructions such as insb, smmul has been rearranged according XLEN.
* removed rv_m in rv32_zbpbp + newline additions
Co-authored-by: Babu P S <babu.ps@incoresemi.com>
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This work is based on Zawrs fast-track extension, version 1.0-rc2.
<https://github.com/riscv/riscv-zawrs/releases/tag/V1.0-rc2>
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This work is based on the latest ISA Manual:
<https://github.com/riscv/riscv-isa-manual/releases/tag/draft-20220622-c3b7d92>
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* Add RV128I instructions
* Address code review feedback
* Fix typo
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- this changes the imports in zk[ns]
- this name is also what spike uses for now.
- This fix may come-back later when zbp and zbkx reconcile on a common naming scheme for these instructions.
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- pseudo ops cannot be imported. The pseudo_op syntax itself should be used where applicable.
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- split instructions as per new file naming policy
- move all instructions to unratified directory
- includes rv[64|32]_zbp[bo] (missed in previous commit while migrating P-extension)
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- includes zbp and zbpbo sub extensions as well
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