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Some of the instructions in the V extension encode part of the opcode
in the rs1 field. These values are not currently included in the Go
instruction opcodes - fix this by adding an rs1 field and populating
it with the relevant values.
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Signed-off-by: Patrick Yingxi Pan <patrick-yingxi-pan@users.noreply.github.com>
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A regression introduced a few years ago prevented detecting partially
overlapping encodings; instead, we only detected exact matches. Now, we
detect the partial cases.
We now need to maintain two allowlists (overlapping_extensions and
overlapping_instructions) for the cases that extensions and/or
instructions overlap by design.
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It is highly speculative at this point, but it adds maintenance burden.
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change decode generation part of chisel
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Add encodings for all instructions in the Zvk extensions:
- Zvbb, Vector Bit-manipulation instructions used in Cryptography,
- Zvbc, Vector Carryless Multiplication
- Zvkg, Vector GCM/GMAC instruction for Cryptography,
- Zvkned, NIST Suite: Vector AES Encryption & Decryption (Single
Round),
- Zvknha, Zvknhb, NIST Suite: Vector SHA-2,
- Zvksed, ShangMi Suite: SM4 Block Cipher Instructions
- Zvkssh, ShangMi Suite: SM3 Hash Function Instructions
Add two "shorthand" extensions:
- Zvkn: NIST Suite, imports Zvbb, Zvbc, Zvkned, and Zvknh
- Zvks: ShangMi Suite, imports Zvbb, Zvbc, Zvksed, and Zvksh
Three new fields are listed in constants.py:
- 'zimm5', used to encode round constants (Zvkns, Zvksed, Zvksh),
and 5-bit shift constant (vwsll.vi in Zvbb)
- 'zimm6hi, zimm6lo', used to encode the 6 bits rotate amount
in vror.vi.
The Zvk instructions – with the exception of Zvbb, Zvbc – reside in the
P opcode space. Some encodings conflict with proposed instructions
in the P extension (packed SIMD). Zvk and P are exclusive of each
other, no implementation will implement both. Conflicting P instructions
are marked as pseudo of the Zvk instructions.
The encodings match the current documentation of the specification
at <https://github.com/riscv/riscv-crypto/tree/master/doc/vector>,
at Version v0.9.1, 25 April, 2023 (Freeze Candidate).
Co-authored-by: Eric Gouriou <ego@rivosinc.com>
Co-authored-by: Stanislaw Kardach <kda@semihalf.com>
Co-authored-by: Kornel Duleba <mindal@semihalf.com>
Co-authored-by: Raghav Gupta <rgupta@rivosinc.com>
Signed-off-by: Eric Gouriou <ego@rivosinc.com>
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Fixes generation of 'extension' field for instr_dict.yaml
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It's a new year. Make the copyright clause reflect 2023.
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This PR changes opcodes_dir to the REAL path of parse.py. It helps python
scripts which depends on parse.py can be stored in other place, using PYTHONPAT
or sys.path to import from riscv-opcodes/parse.
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That allows for running the script out-of-tree.
Signed-off-by: Florian Zaruba <florian@zaruba.email>
Signed-off-by: Florian Zaruba <florian@zaruba.email>
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The BSD-3-Clause license mentions a copyright notice that has to
be retained while redistributing the source code.
Copy the copyright notice from LICENSE file to the script, so it
get in the generated file.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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This removes the language about patents that was added in #133.
Change copyright holder to RISC-V International.
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* fix extension merge and add name and encoding conflict checking
* fix comments
* uniform code's indentation
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Linux kernel coding style requires the SPDX tag to be placed in
the very first line of the generated file. See kernel file
Documentation/process/license-rules.rst
at chapter 'License identifier syntax', '1. Placement:'.
Move the SPDX tag in the python script.
While there, adjust also the style of the multi-line comment.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
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Making a shallow copy of the list prevents updating the final encoding
output when checking for field overlap.
Incorrect:
encoding: 0000000rs2rs2rs2rs2rs2rs1rs1rs1rs1rs1000rdrdrdrdrd0110011
Correct:
encoding: 0000000----------000-----0110011
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specifically done to handle encoding.out.h that is being used by spike
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This is to ensure that pseudo instructions like slli are added from rv64i instead of rv32i
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* Remove duplicate code
* Fix unit test
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* Check for overlapping fields
* Enable unit test
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* Test error inputs handling
* Add mask tests
* Apply code review fix
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* Dump masks to C output
* Use `INSN_FIELD_` for masks
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- the python file is well commented
- the README provides a brief overview of how the python script works and the various artifacts it can generate
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