diff options
Diffstat (limited to 'extensions')
110 files changed, 1618 insertions, 0 deletions
diff --git a/extensions/rv32_c b/extensions/rv32_c new file mode 100644 index 0000000..f8ce289 --- /dev/null +++ b/extensions/rv32_c @@ -0,0 +1,8 @@ +# quadrant 1 +c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 +$pseudo_op rv64_c::c.srli c.srli_rv32 rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai_rv32 rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli_rv32 rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 diff --git a/extensions/rv32_c_f b/extensions/rv32_c_f new file mode 100644 index 0000000..3b735e6 --- /dev/null +++ b/extensions/rv32_c_f @@ -0,0 +1,7 @@ +# quadrant 0 +c.flw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=3 +c.fsw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=7 + +#quadrant 2 +c.flwsp rd c_uimm8sphi c_uimm8splo 1..0=2 15..13=3 +c.fswsp c_rs2 c_uimm8sp_s 1..0=2 15..13=7 diff --git a/extensions/rv32_d_zfa b/extensions/rv32_d_zfa new file mode 100644 index 0000000..8a543e7 --- /dev/null +++ b/extensions/rv32_d_zfa @@ -0,0 +1,2 @@ +fmvh.x.d rd rs1 24..20=1 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +fmvp.d.x rd rs1 rs2 31..27=0x16 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/extensions/rv32_i b/extensions/rv32_i new file mode 100644 index 0000000..59e79da --- /dev/null +++ b/extensions/rv32_i @@ -0,0 +1,6 @@ +$pseudo_op rv64_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::slli slli_rv32 rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli_rv32 rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai_rv32 rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 diff --git a/extensions/rv32_zbb b/extensions/rv32_zbb new file mode 100644 index 0000000..bc23350 --- /dev/null +++ b/extensions/rv32_zbb @@ -0,0 +1,3 @@ +$pseudo_op rv_zbkb::pack zext.h.rv32 rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..0=0x33 +$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 +$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 diff --git a/extensions/rv32_zbkb b/extensions/rv32_zbkb new file mode 100644 index 0000000..55b7be9 --- /dev/null +++ b/extensions/rv32_zbkb @@ -0,0 +1,4 @@ +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 diff --git a/extensions/rv32_zbs b/extensions/rv32_zbs new file mode 100644 index 0000000..fe3c8a2 --- /dev/null +++ b/extensions/rv32_zbs @@ -0,0 +1,4 @@ +$pseudo_op rv64_zbs::bclri bclri.rv32 rd rs1 31..25=0x24 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bexti bexti.rv32 rd rs1 31..25=0x24 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::binvi binvi.rv32 rd rs1 31..25=0x34 shamtw 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_zbs::bseti bseti.rv32 rd rs1 31..25=0x14 shamtw 14..12=1 6..2=0x04 1..0=3 diff --git a/extensions/rv32_zicntr b/extensions/rv32_zicntr new file mode 100644 index 0000000..6df98c3 --- /dev/null +++ b/extensions/rv32_zicntr @@ -0,0 +1,3 @@ +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
diff --git a/extensions/rv32_zk b/extensions/rv32_zk new file mode 100644 index 0000000..b4b1330 --- /dev/null +++ b/extensions/rv32_zk @@ -0,0 +1,24 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h diff --git a/extensions/rv32_zkn b/extensions/rv32_zkn new file mode 100644 index 0000000..b4b1330 --- /dev/null +++ b/extensions/rv32_zkn @@ -0,0 +1,24 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 + +#import zkne +$import rv32_zkne::aes32esmi +$import rv32_zkne::aes32esi + +#import zknd +# Scalar AES - RV32 +$import rv32_zknd::aes32dsmi +$import rv32_zknd::aes32dsi + + +#import zknh +# Scalar SHA512 - RV32 +$import rv32_zknh::sha512sum0r +$import rv32_zknh::sha512sum1r +$import rv32_zknh::sha512sig0l +$import rv32_zknh::sha512sig0h +$import rv32_zknh::sha512sig1l +$import rv32_zknh::sha512sig1h diff --git a/extensions/rv32_zknd b/extensions/rv32_zknd new file mode 100644 index 0000000..aa4bf23 --- /dev/null +++ b/extensions/rv32_zknd @@ -0,0 +1,3 @@ +# Scalar AES - RV32 +aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 +aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 diff --git a/extensions/rv32_zkne b/extensions/rv32_zkne new file mode 100644 index 0000000..c6ac67d --- /dev/null +++ b/extensions/rv32_zkne @@ -0,0 +1,4 @@ +# Scalar AES - RV32 + +aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 +aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 diff --git a/extensions/rv32_zknh b/extensions/rv32_zknh new file mode 100644 index 0000000..501f665 --- /dev/null +++ b/extensions/rv32_zknh @@ -0,0 +1,7 @@ +# Scalar SHA512 - RV32 +sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 +sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 +sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 +sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 +sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 +sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 diff --git a/extensions/rv32_zks b/extensions/rv32_zks new file mode 100644 index 0000000..a422a9b --- /dev/null +++ b/extensions/rv32_zks @@ -0,0 +1,5 @@ +#import zbkb +$pseudo_op rv64_zbp::shfli zip rd rs1 31..25=4 24..20=15 14..12=1 6..2=4 1..0=3 +$pseudo_op rv64_zbp::unshfli unzip rd rs1 31..25=4 24..20=15 14..12=5 6..2=4 1..0=3 +$pseudo_op rv64_zbb::rori rori.rv32 rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbp::grevi rev8.rv32 rd rs1 31..20=0x698 14..12=5 6..0=0x13 diff --git a/extensions/rv64_a b/extensions/rv64_a new file mode 100644 index 0000000..fe208e9 --- /dev/null +++ b/extensions/rv64_a @@ -0,0 +1,12 @@ +# RV64A additions to RV32A +lr.d rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=3 6..2=0x0B 1..0=3 +sc.d rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=3 6..2=0x0B 1..0=3 +amoswap.d rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=3 6..2=0x0B 1..0=3 +amoadd.d rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoxor.d rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoand.d rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amoor.d rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomin.d rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomax.d rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amominu.d rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=3 6..2=0x0B 1..0=3 +amomaxu.d rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=3 6..2=0x0B 1..0=3 diff --git a/extensions/rv64_c b/extensions/rv64_c new file mode 100644 index 0000000..7c7494b --- /dev/null +++ b/extensions/rv64_c @@ -0,0 +1,15 @@ +# quadrant 0 +c.ld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=3 +c.sd rs1_p rs2_p c_uimm8hi c_uimm8lo 1..0=0 15..13=7 + +#quadrant 1 +c.addiw rd_rs1_n0 c_imm6lo c_imm6hi 1..0=1 15..13=1 +c.srli rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=0 +c.srai rd_rs1_p c_nzuimm6lo c_nzuimm6hi 1..0=1 15..13=4 11..10=1 +c.subw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=0 +c.addw rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b111 6..5=1 + +#quadrant 2 +c.slli rd_rs1_n0 c_nzuimm6hi c_nzuimm6lo 1..0=2 15..13=0 +c.ldsp rd_n0 c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 +c.sdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=7 diff --git a/extensions/rv64_d b/extensions/rv64_d new file mode 100644 index 0000000..d8c8299 --- /dev/null +++ b/extensions/rv64_d @@ -0,0 +1,7 @@ +# RV64D additions to RV32D +fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 diff --git a/extensions/rv64_f b/extensions/rv64_f new file mode 100644 index 0000000..64f02d6 --- /dev/null +++ b/extensions/rv64_f @@ -0,0 +1,6 @@ +# RV64F additions to RV32F + +fcvt.l.s rd rs1 24..20=2 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.lu.s rd rs1 24..20=3 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.l rd rs1 24..20=2 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 diff --git a/extensions/rv64_h b/extensions/rv64_h new file mode 100644 index 0000000..75589e1 --- /dev/null +++ b/extensions/rv64_h @@ -0,0 +1,4 @@ +# Hypervisor extension +hlv.wu rd rs1 24..20=0x1 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlv.d rd rs1 24..20=0x0 31..25=0x36 14..12=4 6..2=0x1C 1..0=3 +hsv.d 11..7=0 rs1 rs2 31..25=0x37 14..12=4 6..2=0x1C 1..0=3 diff --git a/extensions/rv64_i b/extensions/rv64_i new file mode 100644 index 0000000..dea3d38 --- /dev/null +++ b/extensions/rv64_i @@ -0,0 +1,22 @@ +# RV64I additions to RV32I + +lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 +ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 +sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 + +slli rd rs1 31..26=0 shamtd 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamtd 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamtd 14..12=5 6..2=0x04 1..0=3 + +addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 +slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 +srliw rd rs1 31..25=0 shamtw 14..12=5 6..2=0x06 1..0=3 +sraiw rd rs1 31..25=32 shamtw 14..12=5 6..2=0x06 1..0=3 + +addw rd rs1 rs2 31..25=0 14..12=0 6..2=0x0E 1..0=3 +subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 +sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 +srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 +sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 + +$pseudo_op rv64_i::addiw sext.w rd rs1 31..20=0 14..12=0 6..2=0x06 1..0=3 diff --git a/extensions/rv64_m b/extensions/rv64_m new file mode 100644 index 0000000..cfac0b1 --- /dev/null +++ b/extensions/rv64_m @@ -0,0 +1,6 @@ +# RV64M additions to RV32M +mulw rd rs1 rs2 31..25=1 14..12=0 6..2=0x0E 1..0=3 +divw rd rs1 rs2 31..25=1 14..12=4 6..2=0x0E 1..0=3 +divuw rd rs1 rs2 31..25=1 14..12=5 6..2=0x0E 1..0=3 +remw rd rs1 rs2 31..25=1 14..12=6 6..2=0x0E 1..0=3 +remuw rd rs1 rs2 31..25=1 14..12=7 6..2=0x0E 1..0=3 diff --git a/extensions/rv64_q b/extensions/rv64_q new file mode 100644 index 0000000..571edf1 --- /dev/null +++ b/extensions/rv64_q @@ -0,0 +1,7 @@ +# RV64Q additions to RV32Q + +fcvt.l.q rd rs1 24..20=2 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.lu.q rd rs1 24..20=3 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 + +fcvt.q.l rd rs1 24..20=2 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 diff --git a/extensions/rv64_q_zfa b/extensions/rv64_q_zfa new file mode 100644 index 0000000..be33e4e --- /dev/null +++ b/extensions/rv64_q_zfa @@ -0,0 +1,2 @@ +fmvh.x.q rd rs1 24..20=1 31..27=0x1C 14..12=0 26..25=3 6..2=0x14 1..0=3 +fmvp.q.x rd rs1 rs2 31..27=0x16 14..12=0 26..25=3 6..2=0x14 1..0=3 diff --git a/extensions/rv64_zacas b/extensions/rv64_zacas new file mode 100644 index 0000000..089fbd6 --- /dev/null +++ b/extensions/rv64_zacas @@ -0,0 +1 @@ +amocas.q rd rs1 rs2 aq rl 31..29=1 28..27=1 14..12=4 6..2=0x0B 1..0=3 diff --git a/extensions/rv64_zba b/extensions/rv64_zba new file mode 100644 index 0000000..3a1186a --- /dev/null +++ b/extensions/rv64_zba @@ -0,0 +1,7 @@ +add.uw rd rs1 rs2 31..25=4 14..12=0 6..2=0x0E 1..0=3 +sh1add.uw rd rs1 rs2 31..25=16 14..12=2 6..2=0x0E 1..0=3 +sh2add.uw rd rs1 rs2 31..25=16 14..12=4 6..2=0x0E 1..0=3 +sh3add.uw rd rs1 rs2 31..25=16 14..12=6 6..2=0x0E 1..0=3 +slli.uw rd rs1 31..26=2 shamtd 14..12=1 6..2=0x06 1..0=3 + +$pseudo_op rv64_zba::add.uw zext.w rd rs1 31..25=4 24..20=0 14..12=0 6..2=0x0E 1..0=3 diff --git a/extensions/rv64_zbb b/extensions/rv64_zbb new file mode 100644 index 0000000..653827f --- /dev/null +++ b/extensions/rv64_zbb @@ -0,0 +1,9 @@ +clzw rd rs1 31..20=0x600 14..12=1 6..2=0x06 1..0=3 +ctzw rd rs1 31..20=0x601 14..12=1 6..2=0x06 1..0=3 +cpopw rd rs1 31..20=0x602 14..12=1 6..2=0x06 1..0=3 +rolw rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0E 1..0=3 +rorw rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0E 1..0=3 +roriw rd rs1 31..25=0x30 shamtw 14..12=5 6..2=0x06 1..0=3 +rori rd rs1 31..26=0x18 shamtd 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_zbkb::packw zext.h rd rs1 31..25=0x04 24..20=0 14..12=0x4 6..2=0xE 1..0=0x3 +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 diff --git a/extensions/rv64_zbkb b/extensions/rv64_zbkb new file mode 100644 index 0000000..b5e0606 --- /dev/null +++ b/extensions/rv64_zbkb @@ -0,0 +1,6 @@ +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +packw rd rs1 rs2 31..25=4 14..12=4 6..2=0x0E 1..0=3 diff --git a/extensions/rv64_zbs b/extensions/rv64_zbs new file mode 100644 index 0000000..4e15b66 --- /dev/null +++ b/extensions/rv64_zbs @@ -0,0 +1,4 @@ +bclri rd rs1 31..26=0x12 shamtd 14..12=1 6..2=0x04 1..0=3 +bexti rd rs1 31..26=0x12 shamtd 14..12=5 6..2=0x04 1..0=3 +binvi rd rs1 31..26=0x1a shamtd 14..12=1 6..2=0x04 1..0=3 +bseti rd rs1 31..26=0x0a shamtd 14..12=1 6..2=0x04 1..0=3 diff --git a/extensions/rv64_zcb b/extensions/rv64_zcb new file mode 100644 index 0000000..8ce4429 --- /dev/null +++ b/extensions/rv64_zcb @@ -0,0 +1,3 @@ +c.zext.w rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=4 + +$pseudo_op rv64_c::c.addiw c.sext.w rd_rs1_n0 15..13=1 12=0 6..2=0 1..0=1 diff --git a/extensions/rv64_zfh b/extensions/rv64_zfh new file mode 100644 index 0000000..5cc9f25 --- /dev/null +++ b/extensions/rv64_zfh @@ -0,0 +1,7 @@ +# RV64Zfh additions to RV32Zfh + +fcvt.l.h rd rs1 24..20=2 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.lu.h rd rs1 24..20=3 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 + +fcvt.h.l rd rs1 24..20=2 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 diff --git a/extensions/rv64_zk b/extensions/rv64_zk new file mode 100644 index 0000000..b59326f --- /dev/null +++ b/extensions/rv64_zk @@ -0,0 +1,27 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbkb::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 diff --git a/extensions/rv64_zkn b/extensions/rv64_zkn new file mode 100644 index 0000000..b59326f --- /dev/null +++ b/extensions/rv64_zkn @@ -0,0 +1,27 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbkb::packw + +#import zkne +# Scalar AES - RV64 +$import rv64_zkne::aes64esm +$import rv64_zkne::aes64es +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 + +#import zknd +# Scalar AES - RV64 +$import rv64_zknd::aes64dsm +$import rv64_zknd::aes64ds +$import rv64_zknd::aes64im + +#import zknh +# Scalar SHA512 - RV64 +$import rv64_zknh::sha512sum0 +$import rv64_zknh::sha512sum1 +$import rv64_zknh::sha512sig0 +$import rv64_zknh::sha512sig1 diff --git a/extensions/rv64_zknd b/extensions/rv64_zknd new file mode 100644 index 0000000..b276658 --- /dev/null +++ b/extensions/rv64_zknd @@ -0,0 +1,6 @@ +# Scalar AES - RV64 +aes64dsm rd rs1 rs2 31..30=0 29..25=0b11111 14..12=0b000 6..0=0x33 +aes64ds rd rs1 rs2 31..30=0 29..25=0b11101 14..12=0b000 6..0=0x33 +aes64ks1i rd rs1 rnum 31..30=0 29..25=0b11000 24=1 14..12=0b001 6..0=0x13 +aes64im rd rs1 31..30=0 29..25=0b11000 24..20=0b0000 14..12=0b001 6..0=0x13 +aes64ks2 rd rs1 rs2 31..30=1 29..25=0b11111 14..12=0b000 6..0=0x33 diff --git a/extensions/rv64_zkne b/extensions/rv64_zkne new file mode 100644 index 0000000..3323b7f --- /dev/null +++ b/extensions/rv64_zkne @@ -0,0 +1,5 @@ +# Scalar AES - RV64 +aes64esm rd rs1 rs2 31..30=0 29..25=0b11011 14..12=0b000 6..0=0x33 +aes64es rd rs1 rs2 31..30=0 29..25=0b11001 14..12=0b000 6..0=0x33 +$import rv64_zknd::aes64ks1i +$import rv64_zknd::aes64ks2 diff --git a/extensions/rv64_zknh b/extensions/rv64_zknh new file mode 100644 index 0000000..468d526 --- /dev/null +++ b/extensions/rv64_zknh @@ -0,0 +1,5 @@ +# Scalar SHA512 - RV64 +sha512sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00100 14..12=1 6..0=0x13 +sha512sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00101 14..12=1 6..0=0x13 +sha512sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00110 14..12=1 6..0=0x13 +sha512sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00111 14..12=1 6..0=0x13 diff --git a/extensions/rv64_zks b/extensions/rv64_zks new file mode 100644 index 0000000..848a283 --- /dev/null +++ b/extensions/rv64_zks @@ -0,0 +1,7 @@ +#import zbkb +$pseudo_op rv64_zbp::grevi rev8 rd rs1 31..20=0x6B8 14..12=5 6..0=0x13 +$import rv64_zbb::rolw +$import rv64_zbb::rorw +$import rv64_zbb::roriw +$import rv64_zbb::rori +$import rv64_zbkb::packw diff --git a/extensions/rv_a b/extensions/rv_a new file mode 100644 index 0000000..1a70e40 --- /dev/null +++ b/extensions/rv_a @@ -0,0 +1,11 @@ +lr.w rd rs1 24..20=0 aq rl 31..29=0 28..27=2 14..12=2 6..2=0x0B 1..0=3 +sc.w rd rs1 rs2 aq rl 31..29=0 28..27=3 14..12=2 6..2=0x0B 1..0=3 +amoswap.w rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=2 6..2=0x0B 1..0=3 +amoadd.w rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoxor.w rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoand.w rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amoor.w rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomin.w rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomax.w rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amominu.w rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=2 6..2=0x0B 1..0=3 +amomaxu.w rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=2 6..2=0x0B 1..0=3 diff --git a/extensions/rv_c b/extensions/rv_c new file mode 100644 index 0000000..6fda454 --- /dev/null +++ b/extensions/rv_c @@ -0,0 +1,28 @@ +# quadrant 0 +c.addi4spn rd_p c_nzuimm10 1..0=0 15..13=0 +c.lw rd_p rs1_p c_uimm7lo c_uimm7hi 1..0=0 15..13=2 +c.sw rs1_p rs2_p c_uimm7lo c_uimm7hi 1..0=0 15..13=6 + +#quadrant 1 +c.nop c_nzimm6hi c_nzimm6lo 1..0=1 15..13=0 11..7=0 +c.addi rd_rs1_n0 c_nzimm6lo c_nzimm6hi 1..0=1 15..13=0 +c.li rd_n0 c_imm6lo c_imm6hi 1..0=1 15..13=2 +c.addi16sp c_nzimm10hi c_nzimm10lo 1..0=1 15..13=3 11..7=2 +c.lui rd_n2 c_nzimm18hi c_nzimm18lo 1..0=1 15..13=3 +c.andi rd_rs1_p c_imm6hi c_imm6lo 1..0=1 15..13=4 11..10=2 +c.sub rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=0 +c.xor rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=1 +c.or rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=2 +c.and rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=0b011 6..5=3 +c.j c_imm12 1..0=1 15..13=5 +c.beqz rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=6 +c.bnez rs1_p c_bimm9lo c_bimm9hi 1..0=1 15..13=7 + +#quadrant 2 +c.lwsp rd_n0 c_uimm8sphi c_uimm8splo 1..0=2 15..13=2 +c.jr rs1_n0 1..0=2 15..13=4 12=0 6..2=0 +c.mv rd_n0 c_rs2_n0 1..0=2 15..13=4 12=0 +c.ebreak 1..0=2 15..13=4 12=1 11..2=0 +c.jalr c_rs1_n0 1..0=2 15..13=4 12=1 6..2=0 +c.add rd_rs1_n0 c_rs2_n0 1..0=2 15..13=4 12=1 +c.swsp c_rs2 c_uimm8sp_s 1..0=2 15..13=6 diff --git a/extensions/rv_c_d b/extensions/rv_c_d new file mode 100644 index 0000000..66d1ad8 --- /dev/null +++ b/extensions/rv_c_d @@ -0,0 +1,7 @@ +#quadrant 0 +c.fld rd_p rs1_p c_uimm8lo c_uimm8hi 1..0=0 15..13=1 +c.fsd rs1_p rs2_p c_uimm8lo c_uimm8hi 1..0=0 15..13=5 + +#quadrant 2 +c.fldsp rd c_uimm9sphi c_uimm9splo 1..0=2 15..13=1 +c.fsdsp c_rs2 c_uimm9sp_s 1..0=2 15..13=5 diff --git a/extensions/rv_c_zicfiss b/extensions/rv_c_zicfiss new file mode 100644 index 0000000..83431c6 --- /dev/null +++ b/extensions/rv_c_zicfiss @@ -0,0 +1,5 @@ +# c.sspush x1 -> c.mop.1 +$pseudo_op rv_zcmop::c.mop.N c.sspush.x1 1..0=1 6..2=0 11..7=1 12=0 15..13=3 + +# c.sspopchk x5 -> c.mop.5 +$pseudo_op rv_zcmop::c.mop.N c.sspopchk.x5 1..0=1 6..2=0 11..7=5 12=0 15..13=3 diff --git a/extensions/rv_c_zihintntl b/extensions/rv_c_zihintntl new file mode 100644 index 0000000..f31177b --- /dev/null +++ b/extensions/rv_c_zihintntl @@ -0,0 +1,4 @@ +$pseudo_op rv_c::c.add c.ntl.p1 1..0=2 6..2=2 11..7=0 15..13=4 12=1 +$pseudo_op rv_c::c.add c.ntl.pall 1..0=2 6..2=3 11..7=0 15..13=4 12=1 +$pseudo_op rv_c::c.add c.ntl.s1 1..0=2 6..2=4 11..7=0 15..13=4 12=1 +$pseudo_op rv_c::c.add c.ntl.all 1..0=2 6..2=5 11..7=0 15..13=4 12=1 diff --git a/extensions/rv_d b/extensions/rv_d new file mode 100644 index 0000000..94cf863 --- /dev/null +++ b/extensions/rv_d @@ -0,0 +1,31 @@ +fld rd rs1 imm12 14..12=3 6..2=0x01 1..0=3 +fsd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x09 1..0=3 +fmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x10 1..0=3 +fmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x11 1..0=3 +fnmsub.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x12 1..0=3 +fnmadd.d rd rs1 rs2 rs3 rm 26..25=1 6..2=0x13 1..0=3 +fadd.d rd rs1 rs2 31..27=0x00 rm 26..25=1 6..2=0x14 1..0=3 +fsub.d rd rs1 rs2 31..27=0x01 rm 26..25=1 6..2=0x14 1..0=3 +fmul.d rd rs1 rs2 31..27=0x02 rm 26..25=1 6..2=0x14 1..0=3 +fdiv.d rd rs1 rs2 31..27=0x03 rm 26..25=1 6..2=0x14 1..0=3 +fsqrt.d rd rs1 24..20=0 31..27=0x0B rm 26..25=1 6..2=0x14 1..0=3 +fsgnj.d rd rs1 rs2 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +fsgnjn.d rd rs1 rs2 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 +fsgnjx.d rd rs1 rs2 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +fmin.d rd rs1 rs2 31..27=0x05 14..12=0 26..25=1 6..2=0x14 1..0=3 +fmax.d rd rs1 rs2 31..27=0x05 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.s.d rd rs1 24..20=1 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.d.s rd rs1 24..20=0 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +feq.d rd rs1 rs2 31..27=0x14 14..12=2 26..25=1 6..2=0x14 1..0=3 +flt.d rd rs1 rs2 31..27=0x14 14..12=1 26..25=1 6..2=0x14 1..0=3 +fle.d rd rs1 rs2 31..27=0x14 14..12=0 26..25=1 6..2=0x14 1..0=3 +fclass.d rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=1 6..2=0x14 1..0=3 +fcvt.w.d rd rs1 24..20=0 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.wu.d rd rs1 24..20=1 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.w rd rs1 24..20=0 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 + +#pseudoinstructions +$pseudo_op rv_d::fsgnj.d fmv.d rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjx.d fabs.d rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=1 6..2=0x14 1..0=3 +$pseudo_op rv_d::fsgnjn.d fneg.d rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=1 6..2=0x14 1..0=3 diff --git a/extensions/rv_d_zfa b/extensions/rv_d_zfa new file mode 100644 index 0000000..7158eef --- /dev/null +++ b/extensions/rv_d_zfa @@ -0,0 +1,8 @@ +fli.d rd rs1 24..20=1 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 +fminm.d rd rs1 rs2 31..27=0x05 14..12=2 26..25=1 6..2=0x14 1..0=3 +fmaxm.d rd rs1 rs2 31..27=0x05 14..12=3 26..25=1 6..2=0x14 1..0=3 +fround.d rd rs1 24..20=4 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +froundnx.d rd rs1 24..20=5 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvtmod.w.d rd rs1 24..20=8 31..27=0x18 14..12=1 26..25=1 6..2=0x14 1..0=3 +fleq.d rd rs1 rs2 31..27=0x14 14..12=4 26..25=1 6..2=0x14 1..0=3 +fltq.d rd rs1 rs2 31..27=0x14 14..12=5 26..25=1 6..2=0x14 1..0=3 diff --git a/extensions/rv_d_zfh b/extensions/rv_d_zfh new file mode 100644 index 0000000..80d3765 --- /dev/null +++ b/extensions/rv_d_zfh @@ -0,0 +1,2 @@ +fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/extensions/rv_f b/extensions/rv_f new file mode 100644 index 0000000..8f37053 --- /dev/null +++ b/extensions/rv_f @@ -0,0 +1,45 @@ +flw rd rs1 imm12 14..12=2 6..2=0x01 1..0=3 +fsw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x09 1..0=3 +fmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x10 1..0=3 +fmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x11 1..0=3 +fnmsub.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x12 1..0=3 +fnmadd.s rd rs1 rs2 rs3 rm 26..25=0 6..2=0x13 1..0=3 +fadd.s rd rs1 rs2 31..27=0x00 rm 26..25=0 6..2=0x14 1..0=3 +fsub.s rd rs1 rs2 31..27=0x01 rm 26..25=0 6..2=0x14 1..0=3 +fmul.s rd rs1 rs2 31..27=0x02 rm 26..25=0 6..2=0x14 1..0=3 +fdiv.s rd rs1 rs2 31..27=0x03 rm 26..25=0 6..2=0x14 1..0=3 +fsqrt.s rd rs1 24..20=0 31..27=0x0B rm 26..25=0 6..2=0x14 1..0=3 +fsgnj.s rd rs1 rs2 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +fsgnjn.s rd rs1 rs2 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 +fsgnjx.s rd rs1 rs2 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +fmin.s rd rs1 rs2 31..27=0x05 14..12=0 26..25=0 6..2=0x14 1..0=3 +fmax.s rd rs1 rs2 31..27=0x05 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.w.s rd rs1 24..20=0 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.wu.s rd rs1 24..20=1 31..27=0x18 rm 26..25=0 6..2=0x14 1..0=3 +fmv.x.w rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +feq.s rd rs1 rs2 31..27=0x14 14..12=2 26..25=0 6..2=0x14 1..0=3 +flt.s rd rs1 rs2 31..27=0x14 14..12=1 26..25=0 6..2=0x14 1..0=3 +fle.s rd rs1 rs2 31..27=0x14 14..12=0 26..25=0 6..2=0x14 1..0=3 +fclass.s rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=0 6..2=0x14 1..0=3 +fcvt.s.w rd rs1 24..20=0 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fcvt.s.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=0 6..2=0x14 1..0=3 +fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 + +#Old names for fmv.x.w/fmv.w.x +$pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 + +#pseudointructions +$pseudo_op rv_f::fsgnj.s fmv.s rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjx.s fabs.s rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=0 6..2=0x14 1..0=3 +$pseudo_op rv_f::fsgnjn.s fneg.s rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=0 6..2=0x14 1..0=3 + +#CSRs +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm5 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm5 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 diff --git a/extensions/rv_f_zfa b/extensions/rv_f_zfa new file mode 100644 index 0000000..045fc27 --- /dev/null +++ b/extensions/rv_f_zfa @@ -0,0 +1,7 @@ +fli.s rd rs1 24..20=1 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +fminm.s rd rs1 rs2 31..27=0x05 14..12=2 26..25=0 6..2=0x14 1..0=3 +fmaxm.s rd rs1 rs2 31..27=0x05 14..12=3 26..25=0 6..2=0x14 1..0=3 +fround.s rd rs1 24..20=4 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +froundnx.s rd rs1 24..20=5 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fleq.s rd rs1 rs2 31..27=0x14 14..12=4 26..25=0 6..2=0x14 1..0=3 +fltq.s rd rs1 rs2 31..27=0x14 14..12=5 26..25=0 6..2=0x14 1..0=3 diff --git a/extensions/rv_h b/extensions/rv_h new file mode 100644 index 0000000..84a361d --- /dev/null +++ b/extensions/rv_h @@ -0,0 +1,14 @@ +# Hypervisor extension +hfence.vvma 11..7=0 rs1 rs2 31..25=0x11 14..12=0 6..2=0x1C 1..0=3 +hfence.gvma 11..7=0 rs1 rs2 31..25=0x31 14..12=0 6..2=0x1C 1..0=3 + +hlv.b rd rs1 24..20=0x0 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.bu rd rs1 24..20=0x1 31..25=0x30 14..12=4 6..2=0x1C 1..0=3 +hlv.h rd rs1 24..20=0x0 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.hu rd rs1 24..20=0x1 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlvx.hu rd rs1 24..20=0x3 31..25=0x32 14..12=4 6..2=0x1C 1..0=3 +hlv.w rd rs1 24..20=0x0 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hlvx.wu rd rs1 24..20=0x3 31..25=0x34 14..12=4 6..2=0x1C 1..0=3 +hsv.b 11..7=0 rs1 rs2 31..25=0x31 14..12=4 6..2=0x1C 1..0=3 +hsv.h 11..7=0 rs1 rs2 31..25=0x33 14..12=4 6..2=0x1C 1..0=3 +hsv.w 11..7=0 rs1 rs2 31..25=0x35 14..12=4 6..2=0x1C 1..0=3 diff --git a/extensions/rv_i b/extensions/rv_i new file mode 100644 index 0000000..6d1fd38 --- /dev/null +++ b/extensions/rv_i @@ -0,0 +1,76 @@ +# rv_i + +lui rd imm20 6..2=0x0D 1..0=3 +auipc rd imm20 6..2=0x05 1..0=3 +jal rd jimm20 6..2=0x1b 1..0=3 +jalr rd rs1 imm12 14..12=0 6..2=0x19 1..0=3 +beq bimm12hi rs1 rs2 bimm12lo 14..12=0 6..2=0x18 1..0=3 +bne bimm12hi rs1 rs2 bimm12lo 14..12=1 6..2=0x18 1..0=3 +blt bimm12hi rs1 rs2 bimm12lo 14..12=4 6..2=0x18 1..0=3 +bge bimm12hi rs1 rs2 bimm12lo 14..12=5 6..2=0x18 1..0=3 +bltu bimm12hi rs1 rs2 bimm12lo 14..12=6 6..2=0x18 1..0=3 +bgeu bimm12hi rs1 rs2 bimm12lo 14..12=7 6..2=0x18 1..0=3 +lb rd rs1 imm12 14..12=0 6..2=0x00 1..0=3 +lh rd rs1 imm12 14..12=1 6..2=0x00 1..0=3 +lw rd rs1 imm12 14..12=2 6..2=0x00 1..0=3 +lbu rd rs1 imm12 14..12=4 6..2=0x00 1..0=3 +lhu rd rs1 imm12 14..12=5 6..2=0x00 1..0=3 +sb imm12hi rs1 rs2 imm12lo 14..12=0 6..2=0x08 1..0=3 +sh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x08 1..0=3 +sw imm12hi rs1 rs2 imm12lo 14..12=2 6..2=0x08 1..0=3 +addi rd rs1 imm12 14..12=0 6..2=0x04 1..0=3 +slti rd rs1 imm12 14..12=2 6..2=0x04 1..0=3 +sltiu rd rs1 imm12 14..12=3 6..2=0x04 1..0=3 +xori rd rs1 imm12 14..12=4 6..2=0x04 1..0=3 +ori rd rs1 imm12 14..12=6 6..2=0x04 1..0=3 +andi rd rs1 imm12 14..12=7 6..2=0x04 1..0=3 +add rd rs1 rs2 31..25=0 14..12=0 6..2=0x0C 1..0=3 +sub rd rs1 rs2 31..25=32 14..12=0 6..2=0x0C 1..0=3 +sll rd rs1 rs2 31..25=0 14..12=1 6..2=0x0C 1..0=3 +slt rd rs1 rs2 31..25=0 14..12=2 6..2=0x0C 1..0=3 +sltu rd rs1 rs2 31..25=0 14..12=3 6..2=0x0C 1..0=3 +xor rd rs1 rs2 31..25=0 14..12=4 6..2=0x0C 1..0=3 +srl rd rs1 rs2 31..25=0 14..12=5 6..2=0x0C 1..0=3 +sra rd rs1 rs2 31..25=32 14..12=5 6..2=0x0C 1..0=3 +or rd rs1 rs2 31..25=0 14..12=6 6..2=0x0C 1..0=3 +and rd rs1 rs2 31..25=0 14..12=7 6..2=0x0C 1..0=3 +fence fm pred succ rs1 14..12=0 rd 6..2=0x03 1..0=3 +#specialized fences +$pseudo_op rv_i::fence fence.tso 31..28=8 27..24=3 23..20=3 rs1 14..12=0 rd 6..2=0x03 1..0=3 +$pseudo_op rv_i::fence pause 31..28=0 27..24=1 23..20=0 19..15=0 14..12=0 11..7=0 6..2=0x03 1..0=3 +ecall 31..20=0x000 19..7=0 6..2=0x1C 1..0=3 +ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 + +#Old names for ecall/ebreak +$pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 +$pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 + + +#pseudoinstructions from asm manual +$pseudo_op rv_i::addi mv rd rs1 31..20=0 14..12=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::sub neg rd rs1 31..25=32 24..20=0x0 14..12=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::addi nop 31..20=0 19..15=0 14..12=0 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::andi zext.b rd rs1 31..20=0xff 14..12=7 6..2=0x04 1..0=3 + +$pseudo_op rv_i::jalr ret 31..20=0 19..15=0x01 14..12=0 11..7=0 6..2=0x19 1..0=3 + +$pseudo_op rv_i::bgeu bleu bimm12hi rs2 rs1 bimm12lo 14..12=7 6..2=0x18 1..0=3 +$pseudo_op rv_i::bltu bgtu bimm12hi rs2 rs1 bimm12lo 14..12=6 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge ble bimm12hi rs2 rs1 bimm12lo 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge bgez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge blez bimm12hi rs2 bimm12lo 19..15=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgt bimm12hi rs2 rs1 bimm12lo 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgtz bimm12hi rs2 bimm12lo 19..15=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bltz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::bne bnez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=1 6..2=0x18 1..0=3 +$pseudo_op rv_i::beq beqz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=0 6..2=0x18 1..0=3 + +$pseudo_op rv_i::sltiu seqz rd rs1 31..20=1 14..12=3 6..2=0x04 1..0=3 +$pseudo_op rv_i::sltu snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3 + +$pseudo_op rv_i::jalr jalr rs1 31..20=0 14..12=0 11..7=0x01 6..2=0x19 1..0=3 +$pseudo_op rv_i::jalr jr rs1 31..20=0 14..12=0 11..7=0x0 6..2=0x19 1..0=3 +$pseudo_op rv_i::jal jal jimm20 11..7=0x01 6..2=0x1b 1..0=3 +$pseudo_op rv_i::jal j jimm20 11..7=0x0 6..2=0x1b 1..0=3 diff --git a/extensions/rv_m b/extensions/rv_m new file mode 100644 index 0000000..51e6786 --- /dev/null +++ b/extensions/rv_m @@ -0,0 +1,8 @@ +mul rd rs1 rs2 31..25=1 14..12=0 6..2=0x0C 1..0=3 +mulh rd rs1 rs2 31..25=1 14..12=1 6..2=0x0C 1..0=3 +mulhsu rd rs1 rs2 31..25=1 14..12=2 6..2=0x0C 1..0=3 +mulhu rd rs1 rs2 31..25=1 14..12=3 6..2=0x0C 1..0=3 +div rd rs1 rs2 31..25=1 14..12=4 6..2=0x0C 1..0=3 +divu rd rs1 rs2 31..25=1 14..12=5 6..2=0x0C 1..0=3 +rem rd rs1 rs2 31..25=1 14..12=6 6..2=0x0C 1..0=3 +remu rd rs1 rs2 31..25=1 14..12=7 6..2=0x0C 1..0=3 diff --git a/extensions/rv_q b/extensions/rv_q new file mode 100644 index 0000000..9e02a60 --- /dev/null +++ b/extensions/rv_q @@ -0,0 +1,34 @@ +flq rd rs1 imm12 14..12=4 6..2=0x01 1..0=3 +fsq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x09 1..0=3 +fmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x10 1..0=3 +fmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x11 1..0=3 +fnmsub.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x12 1..0=3 +fnmadd.q rd rs1 rs2 rs3 rm 26..25=3 6..2=0x13 1..0=3 +fadd.q rd rs1 rs2 31..27=0x00 rm 26..25=3 6..2=0x14 1..0=3 +fsub.q rd rs1 rs2 31..27=0x01 rm 26..25=3 6..2=0x14 1..0=3 +fmul.q rd rs1 rs2 31..27=0x02 rm 26..25=3 6..2=0x14 1..0=3 +fdiv.q rd rs1 rs2 31..27=0x03 rm 26..25=3 6..2=0x14 1..0=3 +fsqrt.q rd rs1 24..20=0 31..27=0x0B rm 26..25=3 6..2=0x14 1..0=3 +fsgnj.q rd rs1 rs2 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +fsgnjn.q rd rs1 rs2 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 +fsgnjx.q rd rs1 rs2 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +fmin.q rd rs1 rs2 31..27=0x05 14..12=0 26..25=3 6..2=0x14 1..0=3 +fmax.q rd rs1 rs2 31..27=0x05 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.s.q rd rs1 24..20=3 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.q.s rd rs1 24..20=0 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.d.q rd rs1 24..20=3 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.q.d rd rs1 24..20=1 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +feq.q rd rs1 rs2 31..27=0x14 14..12=2 26..25=3 6..2=0x14 1..0=3 +flt.q rd rs1 rs2 31..27=0x14 14..12=1 26..25=3 6..2=0x14 1..0=3 +fle.q rd rs1 rs2 31..27=0x14 14..12=0 26..25=3 6..2=0x14 1..0=3 +fclass.q rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=3 6..2=0x14 1..0=3 +fcvt.w.q rd rs1 24..20=0 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.wu.q rd rs1 24..20=1 31..27=0x18 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.w rd rs1 24..20=0 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 +fcvt.q.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=3 6..2=0x14 1..0=3 + + +#pseudoinstructions +$pseudo_op rv_q::fsgnj.q fmv.q rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=3 6..2=0x14 1..0=3 +$pseudo_op rv_q::fsgnjx.q fabs.q rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=3 6..2=0x14 1..0=3 +$pseudo_op rv_q::fsgnjn.q fneg.q rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=3 6..2=0x14 1..0=3 diff --git a/extensions/rv_q_zfa b/extensions/rv_q_zfa new file mode 100644 index 0000000..da45f9d --- /dev/null +++ b/extensions/rv_q_zfa @@ -0,0 +1,7 @@ +fli.q rd rs1 24..20=1 31..27=0x1E 14..12=0 26..25=3 6..2=0x14 1..0=3 +fminm.q rd rs1 rs2 31..27=0x05 14..12=2 26..25=3 6..2=0x14 1..0=3 +fmaxm.q rd rs1 rs2 31..27=0x05 14..12=3 26..25=3 6..2=0x14 1..0=3 +fround.q rd rs1 24..20=4 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +froundnx.q rd rs1 24..20=5 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fleq.q rd rs1 rs2 31..27=0x14 14..12=4 26..25=3 6..2=0x14 1..0=3 +fltq.q rd rs1 rs2 31..27=0x14 14..12=5 26..25=3 6..2=0x14 1..0=3 diff --git a/extensions/rv_q_zfh b/extensions/rv_q_zfh new file mode 100644 index 0000000..24548d5 --- /dev/null +++ b/extensions/rv_q_zfh @@ -0,0 +1,2 @@ +fcvt.q.h rd rs1 24..20=2 31..27=0x08 rm 26..25=3 6..2=0x14 1..0=3 +fcvt.h.q rd rs1 24..20=3 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 diff --git a/extensions/rv_s b/extensions/rv_s new file mode 100644 index 0000000..8f871a2 --- /dev/null +++ b/extensions/rv_s @@ -0,0 +1,2 @@ +sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_sdext b/extensions/rv_sdext new file mode 100644 index 0000000..ea1c3ef --- /dev/null +++ b/extensions/rv_sdext @@ -0,0 +1,2 @@ +# debug +dret 11..7=0 19..15=0 31..20=0x7b2 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_smrnmi b/extensions/rv_smrnmi new file mode 100644 index 0000000..db714a3 --- /dev/null +++ b/extensions/rv_smrnmi @@ -0,0 +1 @@ +mnret 11..7=0 19..15=0 31..20=0x702 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_ssctr b/extensions/rv_ssctr new file mode 100644 index 0000000..49dd9a0 --- /dev/null +++ b/extensions/rv_ssctr @@ -0,0 +1 @@ +sctrclr 11..7=0 19..15=0 31..20=0x104 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_svinval b/extensions/rv_svinval new file mode 100644 index 0000000..cb74e35 --- /dev/null +++ b/extensions/rv_svinval @@ -0,0 +1,4 @@ +# Svinval +sinval.vma 11..7=0 rs1 rs2 31..25=0x0b 14..12=0 6..2=0x1C 1..0=3 +sfence.w.inval 11..7=0 19..15=0x0 24..20=0x0 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 +sfence.inval.ir 11..7=0 19..15=0x0 24..20=0x1 31..25=0x0c 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_svinval_h b/extensions/rv_svinval_h new file mode 100644 index 0000000..07085f9 --- /dev/null +++ b/extensions/rv_svinval_h @@ -0,0 +1,3 @@ +# Svinval +hinval.vvma 11..7=0 rs1 rs2 31..25=0x13 14..12=0 6..2=0x1C 1..0=3 +hinval.gvma 11..7=0 rs1 rs2 31..25=0x33 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_system b/extensions/rv_system new file mode 100644 index 0000000..f21aa34 --- /dev/null +++ b/extensions/rv_system @@ -0,0 +1,3 @@ +# SYSTEM +mret 11..7=0 19..15=0 31..20=0x302 14..12=0 6..2=0x1C 1..0=3 +wfi 11..7=0 19..15=0 31..20=0x105 14..12=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_v b/extensions/rv_v new file mode 100644 index 0000000..b40b860 --- /dev/null +++ b/extensions/rv_v @@ -0,0 +1,451 @@ +# format of a line in this file: +# <instruction name> <args> <opcode> +# +# <opcode> is given by specifying one or more range/value pairs: +# hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) +# +# <args> is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 + +# configuration setting +# https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc +vsetivli 31=1 30=1 zimm10 zimm5 14..12=0x7 rd 6..0=0x57 +vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 +vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 + +# +# Vector Loads and Store +# https://github.com/riscv/riscv-v-spec/blob/master/vmem-format.adoc +# +# Vector Unit-Stride Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#74-vector-unit-stride-instructions +vlm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +vsm.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 +vle8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vd 6..0=0x07 +vle16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vd 6..0=0x07 +vle32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vd 6..0=0x07 +vle64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vd 6..0=0x07 +vse8.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x0 vs3 6..0=0x27 +vse16.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x5 vs3 6..0=0x27 +vse32.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x6 vs3 6..0=0x27 +vse64.v nf 28=0 27..26=0 vm 24..20=0 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Unordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vluxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vluxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vluxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vluxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsuxei8.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsuxei16.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsuxei32.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsuxei64.v nf 28=0 27..26=1 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Strided Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#75-vector-strided-instructions +vlse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vd 6..0=0x07 +vlse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vd 6..0=0x07 +vlse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vd 6..0=0x07 +vlse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vd 6..0=0x07 +vsse8.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsse16.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsse32.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsse64.v nf 28=0 27..26=2 vm rs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Vector Indexed-Ordered Instructions (including segment part) +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#76-vector-indexed-instructions +vloxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vd 6..0=0x07 +vloxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vd 6..0=0x07 +vloxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vd 6..0=0x07 +vloxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vd 6..0=0x07 +vsoxei8.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x0 vs3 6..0=0x27 +vsoxei16.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x5 vs3 6..0=0x27 +vsoxei32.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x6 vs3 6..0=0x27 +vsoxei64.v nf 28=0 27..26=3 vm vs2 rs1 14..12=0x7 vs3 6..0=0x27 + +# Unit-stride Fault-Only-First Loads +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#77-unit-stride-fault-only-first-loads +vle8ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x0 vd 6..0=0x07 +vle16ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x5 vd 6..0=0x07 +vle32ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x6 vd 6..0=0x07 +vle64ff.v nf 28=0 27..26=0 vm 24..20=0x10 rs1 14..12=0x7 vd 6..0=0x07 + +# Vector Load/Store Whole Registers +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#79-vector-loadstore-whole-register-instructions +vl1re8.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl1re16.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl1re32.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl1re64.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl2re8.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl2re16.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl2re32.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl2re64.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl4re8.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl4re16.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl4re32.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl4re64.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vl8re8.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +vl8re16.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x5 vd 6..0=0x07 +vl8re32.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x6 vd 6..0=0x07 +vl8re64.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x7 vd 6..0=0x07 +vs1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 +vs8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vs3 6..0=0x27 + +# Vector Floating-Point Instructions +# https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#14-vector-floating-point-instructions +# OPFVF +vfadd.vf 31..26=0x00 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsub.vf 31..26=0x02 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmin.vf 31..26=0x04 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmax.vf 31..26=0x06 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnj.vf 31..26=0x08 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjn.vf 31..26=0x09 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfsgnjx.vf 31..26=0x0a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1up.vf 31..26=0x0e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfslide1down.vf 31..26=0x0f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.s.f 31..26=0x10 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 + +vfmerge.vfm 31..26=0x17 25=0 vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmv.v.f 31..26=0x17 25=1 24..20=0 rs1 14..12=0x5 vd 6..0=0x57 +vmfeq.vf 31..26=0x18 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfle.vf 31..26=0x19 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmflt.vf 31..26=0x1b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfne.vf 31..26=0x1c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfgt.vf 31..26=0x1d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vmfge.vf 31..26=0x1f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfdiv.vf 31..26=0x20 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrdiv.vf 31..26=0x21 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmul.vf 31..26=0x24 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfrsub.vf 31..26=0x27 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmadd.vf 31..26=0x28 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmadd.vf 31..26=0x29 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsub.vf 31..26=0x2a vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsub.vf 31..26=0x2b vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmacc.vf 31..26=0x2c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmacc.vf 31..26=0x2d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfmsac.vf 31..26=0x2e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfnmsac.vf 31..26=0x2f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +vfwadd.vf 31..26=0x30 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.vf 31..26=0x32 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwadd.wf 31..26=0x34 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwsub.wf 31..26=0x36 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmul.vf 31..26=0x38 vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmacc.vf 31..26=0x3c vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmacc.vf 31..26=0x3d vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwmsac.vf 31..26=0x3e vm vs2 rs1 14..12=0x5 vd 6..0=0x57 +vfwnmsac.vf 31..26=0x3f vm vs2 rs1 14..12=0x5 vd 6..0=0x57 + +# OPFVV +vfadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredusum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredosum.vs 31..26=0x03 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmin.vv 31..26=0x04 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmax.vv 31..26=0x06 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnj.vv 31..26=0x08 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjn.vv 31..26=0x09 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfsgnjx.vv 31..26=0x0a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmv.f.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x1 rd 6..0=0x57 + +vmfeq.vv 31..26=0x18 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfle.vv 31..26=0x19 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmflt.vv 31..26=0x1b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vmfne.vv 31..26=0x1c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfdiv.vv 31..26=0x20 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmul.vv 31..26=0x24 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmadd.vv 31..26=0x28 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsub.vv 31..26=0x2a vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmacc.vv 31..26=0x2c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfmsac.vv 31..26=0x2e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +vfcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x01 14..12=0x1 vd 6..0=0x57 +vfcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x02 14..12=0x1 vd 6..0=0x57 +vfcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x03 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x06 14..12=0x1 vd 6..0=0x57 +vfcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x07 14..12=0x1 vd 6..0=0x57 + +vfwcvt.xu.f.v 31..26=0x12 vm vs2 19..15=0x08 14..12=0x1 vd 6..0=0x57 +vfwcvt.x.f.v 31..26=0x12 vm vs2 19..15=0x09 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.xu.v 31..26=0x12 vm vs2 19..15=0x0A 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.x.v 31..26=0x12 vm vs2 19..15=0x0B 14..12=0x1 vd 6..0=0x57 +vfwcvt.f.f.v 31..26=0x12 vm vs2 19..15=0x0C 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.xu.f.v 31..26=0x12 vm vs2 19..15=0x0E 14..12=0x1 vd 6..0=0x57 +vfwcvt.rtz.x.f.v 31..26=0x12 vm vs2 19..15=0x0F 14..12=0x1 vd 6..0=0x57 + +vfncvt.xu.f.w 31..26=0x12 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 +vfncvt.x.f.w 31..26=0x12 vm vs2 19..15=0x11 14..12=0x1 vd 6..0=0x57 +vfncvt.f.xu.w 31..26=0x12 vm vs2 19..15=0x12 14..12=0x1 vd 6..0=0x57 +vfncvt.f.x.w 31..26=0x12 vm vs2 19..15=0x13 14..12=0x1 vd 6..0=0x57 +vfncvt.f.f.w 31..26=0x12 vm vs2 19..15=0x14 14..12=0x1 vd 6..0=0x57 +vfncvt.rod.f.f.w 31..26=0x12 vm vs2 19..15=0x15 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.xu.f.w 31..26=0x12 vm vs2 19..15=0x16 14..12=0x1 vd 6..0=0x57 +vfncvt.rtz.x.f.w 31..26=0x12 vm vs2 19..15=0x17 14..12=0x1 vd 6..0=0x57 + +vfsqrt.v 31..26=0x13 vm vs2 19..15=0x00 14..12=0x1 vd 6..0=0x57 +vfrsqrt7.v 31..26=0x13 vm vs2 19..15=0x04 14..12=0x1 vd 6..0=0x57 +vfrec7.v 31..26=0x13 vm vs2 19..15=0x05 14..12=0x1 vd 6..0=0x57 +vfclass.v 31..26=0x13 vm vs2 19..15=0x10 14..12=0x1 vd 6..0=0x57 + +vfwadd.vv 31..26=0x30 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredusum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.vv 31..26=0x32 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwredosum.vs 31..26=0x33 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwadd.wv 31..26=0x34 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwsub.wv 31..26=0x36 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmul.vv 31..26=0x38 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmacc.vv 31..26=0x3c vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmsac.vv 31..26=0x3e vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwnmsac.vv 31..26=0x3f vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +# OPIVX +vadd.vx 31..26=0x00 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsub.vx 31..26=0x02 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrsub.vx 31..26=0x03 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vminu.vx 31..26=0x04 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmin.vx 31..26=0x05 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmaxu.vx 31..26=0x06 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmax.vx 31..26=0x07 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vand.vx 31..26=0x09 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vor.vx 31..26=0x0a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vxor.vx 31..26=0x0b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vrgather.vx 31..26=0x0c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslideup.vx 31..26=0x0e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vslidedown.vx 31..26=0x0f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vadc.vxm 31..26=0x10 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vxm 31..26=0x11 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmadc.vx 31..26=0x11 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsbc.vxm 31..26=0x12 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vxm 31..26=0x13 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsbc.vx 31..26=0x13 25=1 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmerge.vxm 31..26=0x17 25=0 vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmv.v.x 31..26=0x17 25=1 24..20=0 rs1 14..12=0x4 vd 6..0=0x57 +vmseq.vx 31..26=0x18 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsne.vx 31..26=0x19 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsltu.vx 31..26=0x1a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmslt.vx 31..26=0x1b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsleu.vx 31..26=0x1c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsle.vx 31..26=0x1d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgtu.vx 31..26=0x1e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vmsgt.vx 31..26=0x1f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +vsaddu.vx 31..26=0x20 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsadd.vx 31..26=0x21 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssubu.vx 31..26=0x22 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssub.vx 31..26=0x23 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsll.vx 31..26=0x25 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsmul.vx 31..26=0x27 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsrl.vx 31..26=0x28 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vsra.vx 31..26=0x29 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssrl.vx 31..26=0x2a vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vssra.vx 31..26=0x2b vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsrl.wx 31..26=0x2c vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnsra.wx 31..26=0x2d vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclipu.wx 31..26=0x2e vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vnclip.wx 31..26=0x2f vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +# OPIVV +vadd.vv 31..26=0x00 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsub.vv 31..26=0x02 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vminu.vv 31..26=0x04 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmin.vv 31..26=0x05 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmaxu.vv 31..26=0x06 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmax.vv 31..26=0x07 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vand.vv 31..26=0x09 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vor.vv 31..26=0x0a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vxor.vv 31..26=0x0b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgather.vv 31..26=0x0c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrgatherei16.vv 31..26=0x0e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vadc.vvm 31..26=0x10 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vvm 31..26=0x11 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmadc.vv 31..26=0x11 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsbc.vvm 31..26=0x12 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vvm 31..26=0x13 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsbc.vv 31..26=0x13 25=1 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmerge.vvm 31..26=0x17 25=0 vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmv.v.v 31..26=0x17 25=1 24..20=0 vs1 14..12=0x0 vd 6..0=0x57 +vmseq.vv 31..26=0x18 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsne.vv 31..26=0x19 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsltu.vv 31..26=0x1a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmslt.vv 31..26=0x1b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsleu.vv 31..26=0x1c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vmsle.vv 31..26=0x1d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vsaddu.vv 31..26=0x20 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsadd.vv 31..26=0x21 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssubu.vv 31..26=0x22 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssub.vv 31..26=0x23 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsll.vv 31..26=0x25 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsmul.vv 31..26=0x27 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsrl.vv 31..26=0x28 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vsra.vv 31..26=0x29 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssrl.vv 31..26=0x2a vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vssra.vv 31..26=0x2b vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsrl.wv 31..26=0x2c vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnsra.wv 31..26=0x2d vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclipu.wv 31..26=0x2e vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vnclip.wv 31..26=0x2f vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +vwredsumu.vs 31..26=0x30 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 + +# OPIVI +vadd.vi 31..26=0x00 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrsub.vi 31..26=0x03 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vand.vi 31..26=0x09 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vor.vi 31..26=0x0a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vxor.vi 31..26=0x0b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vrgather.vi 31..26=0x0c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslideup.vi 31..26=0x0e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vslidedown.vi 31..26=0x0f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vadc.vim 31..26=0x10 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vim 31..26=0x11 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmadc.vi 31..26=0x11 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmerge.vim 31..26=0x17 25=0 vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv.v.i 31..26=0x17 25=1 24..20=0 simm5 14..12=0x3 vd 6..0=0x57 +vmseq.vi 31..26=0x18 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsne.vi 31..26=0x19 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsleu.vi 31..26=0x1c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsle.vi 31..26=0x1d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgtu.vi 31..26=0x1e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmsgt.vi 31..26=0x1f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +vsaddu.vi 31..26=0x20 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsadd.vi 31..26=0x21 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsll.vi 31..26=0x25 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vmv1r.v 31..26=0x27 25=1 vs2 19..15=0 14..12=0x3 vd 6..0=0x57 +vmv2r.v 31..26=0x27 25=1 vs2 19..15=1 14..12=0x3 vd 6..0=0x57 +vmv4r.v 31..26=0x27 25=1 vs2 19..15=3 14..12=0x3 vd 6..0=0x57 +vmv8r.v 31..26=0x27 25=1 vs2 19..15=7 14..12=0x3 vd 6..0=0x57 +vsrl.vi 31..26=0x28 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vsra.vi 31..26=0x29 vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssrl.vi 31..26=0x2a vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vssra.vi 31..26=0x2b vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsrl.wi 31..26=0x2c vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnsra.wi 31..26=0x2d vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclipu.wi 31..26=0x2e vm vs2 simm5 14..12=0x3 vd 6..0=0x57 +vnclip.wi 31..26=0x2f vm vs2 simm5 14..12=0x3 vd 6..0=0x57 + +# OPMVV +vredsum.vs 31..26=0x00 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredand.vs 31..26=0x01 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredor.vs 31..26=0x02 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredxor.vs 31..26=0x03 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredminu.vs 31..26=0x04 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmin.vs 31..26=0x05 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmaxu.vs 31..26=0x06 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vredmax.vs 31..26=0x07 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaaddu.vv 31..26=0x08 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vaadd.vv 31..26=0x09 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasubu.vv 31..26=0x0a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vasub.vv 31..26=0x0b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmv.x.s 31..26=0x10 25=1 vs2 19..15=0 14..12=0x2 rd 6..0=0x57 + +# Vector Integer Extension Instructions +# https://github.com/riscv/riscv-v-spec/blob/e49574c92b072fd4d71e6cb20f7e8154de5b83fe/v-spec.adoc#123-vector-integer-extension +vzext.vf8 31..26=0x12 vm vs2 19..15=2 14..12=0x2 vd 6..0=0x57 +vsext.vf8 31..26=0x12 vm vs2 19..15=3 14..12=0x2 vd 6..0=0x57 +vzext.vf4 31..26=0x12 vm vs2 19..15=4 14..12=0x2 vd 6..0=0x57 +vsext.vf4 31..26=0x12 vm vs2 19..15=5 14..12=0x2 vd 6..0=0x57 +vzext.vf2 31..26=0x12 vm vs2 19..15=6 14..12=0x2 vd 6..0=0x57 +vsext.vf2 31..26=0x12 vm vs2 19..15=7 14..12=0x2 vd 6..0=0x57 + +vcompress.vm 31..26=0x17 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmandn.mm 31..26=0x18 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmand.mm 31..26=0x19 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmor.mm 31..26=0x1a 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxor.mm 31..26=0x1b 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmorn.mm 31..26=0x1c 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnand.mm 31..26=0x1d 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmnor.mm 31..26=0x1e 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmxnor.mm 31..26=0x1f 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vmsbf.m 31..26=0x14 vm vs2 19..15=0x01 14..12=0x2 vd 6..0=0x57 +vmsof.m 31..26=0x14 vm vs2 19..15=0x02 14..12=0x2 vd 6..0=0x57 +vmsif.m 31..26=0x14 vm vs2 19..15=0x03 14..12=0x2 vd 6..0=0x57 +viota.m 31..26=0x14 vm vs2 19..15=0x10 14..12=0x2 vd 6..0=0x57 +vid.v 31..26=0x14 vm 24..20=0 19..15=0x11 14..12=0x2 vd 6..0=0x57 +vcpop.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 +vfirst.m 31..26=0x10 vm vs2 19..15=0x11 14..12=0x2 rd 6..0=0x57 + +vdivu.vv 31..26=0x20 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vdiv.vv 31..26=0x21 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vremu.vv 31..26=0x22 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vrem.vv 31..26=0x23 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhu.vv 31..26=0x24 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmul.vv 31..26=0x25 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulhsu.vv 31..26=0x26 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmulh.vv 31..26=0x27 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmadd.vv 31..26=0x29 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsub.vv 31..26=0x2b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vmacc.vv 31..26=0x2d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vnmsac.vv 31..26=0x2f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +vwaddu.vv 31..26=0x30 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.vv 31..26=0x31 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.vv 31..26=0x32 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.vv 31..26=0x33 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwaddu.wv 31..26=0x34 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwadd.wv 31..26=0x35 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsubu.wv 31..26=0x36 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwsub.wv 31..26=0x37 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulu.vv 31..26=0x38 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmulsu.vv 31..26=0x3a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmul.vv 31..26=0x3b vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccu.vv 31..26=0x3c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmacc.vv 31..26=0x3d vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vwmaccsu.vv 31..26=0x3f vm vs2 vs1 14..12=0x2 vd 6..0=0x57 + +# OPMVX +vaaddu.vx 31..26=0x08 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vaadd.vx 31..26=0x09 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasubu.vx 31..26=0x0a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vasub.vx 31..26=0x0b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vmv.s.x 31..26=0x10 25=1 24..20=0 rs1 14..12=0x6 vd 6..0=0x57 +vslide1up.vx 31..26=0x0e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vslide1down.vx 31..26=0x0f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vdivu.vx 31..26=0x20 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vdiv.vx 31..26=0x21 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vremu.vx 31..26=0x22 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vrem.vx 31..26=0x23 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhu.vx 31..26=0x24 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmul.vx 31..26=0x25 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulhsu.vx 31..26=0x26 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmulh.vx 31..26=0x27 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmadd.vx 31..26=0x29 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsub.vx 31..26=0x2b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vmacc.vx 31..26=0x2d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vnmsac.vx 31..26=0x2f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +vwaddu.vx 31..26=0x30 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.vx 31..26=0x31 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.vx 31..26=0x32 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.vx 31..26=0x33 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwaddu.wx 31..26=0x34 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwadd.wx 31..26=0x35 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsubu.wx 31..26=0x36 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwsub.wx 31..26=0x37 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulu.vx 31..26=0x38 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmulsu.vx 31..26=0x3a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmul.vx 31..26=0x3b vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccu.vx 31..26=0x3c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmacc.vx 31..26=0x3d vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccus.vx 31..26=0x3e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vwmaccsu.vx 31..26=0x3f vm vs2 rs1 14..12=0x6 vd 6..0=0x57 diff --git a/extensions/rv_v_aliases b/extensions/rv_v_aliases new file mode 100644 index 0000000..0f7aaa6 --- /dev/null +++ b/extensions/rv_v_aliases @@ -0,0 +1,18 @@ +# vmv1r.v, vmv2r.v, vmv4r.v, vmv8r.v +#@vmvnfr.v 31..26=0x27 25=1 vs2 simm5 14..12=0x3 vd 6..0=0x57 + +$pseudo_op rv_v::vl1re8.v vl1r.v 31..29=0 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl2re8.v vl2r.v 31..29=1 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl4re8.v vl4r.v 31..29=3 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vl8re8.v vl8r.v 31..29=7 28=0 27..26=0 25=1 24..20=0x08 rs1 14..12=0x0 vd 6..0=0x07 + +$pseudo_op rv_v::vlm.v vle1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vd 6..0=0x07 +$pseudo_op rv_v::vsm.v vse1.v 31..28=0 27..26=0 25=1 24..20=0xb rs1 14..12=0x0 vs3 6..0=0x27 + +$pseudo_op rv_v::vfredusum.vs vfredsum.vs 31..26=0x01 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +$pseudo_op rv_v::vfwredusum.vs vfwredsum.vs 31..26=0x31 vm vs2 vs1 14..12=0x1 vd 6..0=0x57 + +$pseudo_op rv_v::vcpop.m vpopc.m 31..26=0x10 vm vs2 19..15=0x10 14..12=0x2 rd 6..0=0x57 + +$pseudo_op rv_v::vmorn.mm vmornot.mm 31..26=0x1c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +$pseudo_op rv_v::vmandn.mm vmandnot.mm 31..26=0x18 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 diff --git a/extensions/rv_zabha b/extensions/rv_zabha new file mode 100644 index 0000000..b3a6f79 --- /dev/null +++ b/extensions/rv_zabha @@ -0,0 +1,23 @@ +# byte width AMO +amoswap.b rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=0 6..2=0x0B 1..0=3 +amoadd.b rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amoxor.b rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amoand.b rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amoor.b rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amomin.b rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amomax.b rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amominu.b rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amomaxu.b rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=0 6..2=0x0B 1..0=3 +amocas.b rd rs1 rs2 aq rl 31..29=1 28..27=1 14..12=0 6..2=0x0B 1..0=3 + +# halfword width AMO +amoswap.h rd rs1 rs2 aq rl 31..29=0 28..27=1 14..12=1 6..2=0x0B 1..0=3 +amoadd.h rd rs1 rs2 aq rl 31..29=0 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amoxor.h rd rs1 rs2 aq rl 31..29=1 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amoand.h rd rs1 rs2 aq rl 31..29=3 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amoor.h rd rs1 rs2 aq rl 31..29=2 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amomin.h rd rs1 rs2 aq rl 31..29=4 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amomax.h rd rs1 rs2 aq rl 31..29=5 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amominu.h rd rs1 rs2 aq rl 31..29=6 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amomaxu.h rd rs1 rs2 aq rl 31..29=7 28..27=0 14..12=1 6..2=0x0B 1..0=3 +amocas.h rd rs1 rs2 aq rl 31..29=1 28..27=1 14..12=1 6..2=0x0B 1..0=3 diff --git a/extensions/rv_zacas b/extensions/rv_zacas new file mode 100644 index 0000000..f9bb1e8 --- /dev/null +++ b/extensions/rv_zacas @@ -0,0 +1,2 @@ +amocas.w rd rs1 rs2 aq rl 31..29=1 28..27=1 14..12=2 6..2=0x0B 1..0=3 +amocas.d rd rs1 rs2 aq rl 31..29=1 28..27=1 14..12=3 6..2=0x0B 1..0=3 diff --git a/extensions/rv_zawrs b/extensions/rv_zawrs new file mode 100644 index 0000000..00c260d --- /dev/null +++ b/extensions/rv_zawrs @@ -0,0 +1,2 @@ +wrs.nto 31..20=0x00D 19..7=0 6..2=0x1C 1..0=3 +wrs.sto 31..20=0x01D 19..7=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_zba b/extensions/rv_zba new file mode 100644 index 0000000..65eb420 --- /dev/null +++ b/extensions/rv_zba @@ -0,0 +1,3 @@ +sh1add rd rs1 rs2 31..25=16 14..12=2 6..2=0x0C 1..0=3 +sh2add rd rs1 rs2 31..25=16 14..12=4 6..2=0x0C 1..0=3 +sh3add rd rs1 rs2 31..25=16 14..12=6 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zbb b/extensions/rv_zbb new file mode 100644 index 0000000..9f384f6 --- /dev/null +++ b/extensions/rv_zbb @@ -0,0 +1,15 @@ +andn rd rs1 rs2 31..25=32 14..12=7 6..2=0x0C 1..0=3 +orn rd rs1 rs2 31..25=32 14..12=6 6..2=0x0C 1..0=3 +xnor rd rs1 rs2 31..25=32 14..12=4 6..2=0x0C 1..0=3 +clz rd rs1 31..20=0x600 14..12=1 6..2=0x04 1..0=3 +ctz rd rs1 31..20=0x601 14..12=1 6..2=0x04 1..0=3 +cpop rd rs1 31..20=0x602 14..12=1 6..2=0x04 1..0=3 +max rd rs1 rs2 31..25=5 14..12=6 6..2=0x0C 1..0=3 +maxu rd rs1 rs2 31..25=5 14..12=7 6..2=0x0C 1..0=3 +min rd rs1 rs2 31..25=5 14..12=4 6..2=0x0C 1..0=3 +minu rd rs1 rs2 31..25=5 14..12=5 6..2=0x0C 1..0=3 +sext.b rd rs1 31..20=0x604 14..12=1 6..2=0x04 1..0=3 +sext.h rd rs1 31..20=0x605 14..12=1 6..2=0x04 1..0=3 +rol rd rs1 rs2 31..25=0x30 14..12=1 6..2=0x0C 1..0=3 +ror rd rs1 rs2 31..25=0x30 14..12=5 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::gorci orc.b rd rs1 31..20=0x287 14..12=0x5 6..0=0x13 diff --git a/extensions/rv_zbc b/extensions/rv_zbc new file mode 100644 index 0000000..821518b --- /dev/null +++ b/extensions/rv_zbc @@ -0,0 +1,3 @@ +clmul rd rs1 rs2 31..25=5 14..12=1 6..2=0x0C 1..0=3 +clmulr rd rs1 rs2 31..25=5 14..12=2 6..2=0x0C 1..0=3 +clmulh rd rs1 rs2 31..25=5 14..12=3 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zbkb b/extensions/rv_zbkb new file mode 100644 index 0000000..d3f2f8d --- /dev/null +++ b/extensions/rv_zbkb @@ -0,0 +1,8 @@ +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +pack rd rs1 rs2 31..25=4 14..12=4 6..2=0x0C 1..0=3 +packh rd rs1 rs2 31..25=4 14..12=7 6..2=0x0C 1..0=3 +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 diff --git a/extensions/rv_zbkc b/extensions/rv_zbkc new file mode 100644 index 0000000..b82588f --- /dev/null +++ b/extensions/rv_zbkc @@ -0,0 +1,2 @@ +$import rv_zbc::clmul +$import rv_zbc::clmulh diff --git a/extensions/rv_zbkx b/extensions/rv_zbkx new file mode 100644 index 0000000..12bc0b4 --- /dev/null +++ b/extensions/rv_zbkx @@ -0,0 +1,2 @@ +xperm4 rd rs1 rs2 31..25=20 14..12=2 6..2=0x0C 1..0=3 +xperm8 rd rs1 rs2 31..25=20 14..12=4 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zbs b/extensions/rv_zbs new file mode 100644 index 0000000..3dd77eb --- /dev/null +++ b/extensions/rv_zbs @@ -0,0 +1,4 @@ +bclr rd rs1 rs2 31..25=0x24 14..12=1 6..2=0x0C 1..0=3 +bext rd rs1 rs2 31..25=36 14..12=5 6..2=0x0C 1..0=3 +binv rd rs1 rs2 31..25=52 14..12=1 6..2=0x0C 1..0=3 +bset rd rs1 rs2 31..25=20 14..12=1 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zcb b/extensions/rv_zcb new file mode 100644 index 0000000..2e65437 --- /dev/null +++ b/extensions/rv_zcb @@ -0,0 +1,11 @@ +c.lbu rd_p rs1_p c_uimm2 1..0=0 15..13=4 12..10=0 +c.lhu rd_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=1 6=0 +c.lh rd_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=1 6=1 +c.sb rs2_p rs1_p c_uimm2 1..0=0 15..13=4 12..10=2 +c.sh rs2_p rs1_p c_uimm1 1..0=0 15..13=4 12..10=3 6=0 +c.zext.b rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=0 +c.sext.b rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=1 +c.zext.h rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=2 +c.sext.h rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=3 +c.not rd_rs1_p 1..0=1 15..13=4 12..10=7 6..5=3 4..2=5 +c.mul rd_rs1_p rs2_p 1..0=1 15..13=4 12..10=7 6..5=2 diff --git a/extensions/rv_zcmop b/extensions/rv_zcmop new file mode 100644 index 0000000..742a3d8 --- /dev/null +++ b/extensions/rv_zcmop @@ -0,0 +1,15 @@ +# Eight code points in the 16-bit encoding space +# are provided for MOPs; c.mop.N is encoded in +# the reserved encoding space where c.lui N, 0 is +# encoded. N ={1, 3, 5, 7, 9, 11, 13, and 15} +# Add a pseudo-inst c.mop.N that matches c.mop.* + +c.mop.N c_mop_t 1..0=1 6..2=0 11=0 7=1 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.1 1..0=1 6..2=0 11..7=1 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.3 1..0=1 6..2=0 11..7=3 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.5 1..0=1 6..2=0 11..7=5 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.7 1..0=1 6..2=0 11..7=7 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.9 1..0=1 6..2=0 11..7=9 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.11 1..0=1 6..2=0 11..7=11 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.13 1..0=1 6..2=0 11..7=13 12=0 15..13=3 +$pseudo_op rv_zcmop::c.mop.N c.mop.15 1..0=1 6..2=0 11..7=15 12=0 15..13=3 diff --git a/extensions/rv_zcmp b/extensions/rv_zcmp new file mode 100644 index 0000000..c72d1de --- /dev/null +++ b/extensions/rv_zcmp @@ -0,0 +1,6 @@ +cm.push c_rlist c_spimm 1..0=2 15..13=5 12..8=0x18 +cm.pop c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1A +cm.popretz c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1C +cm.popret c_rlist c_spimm 1..0=2 15..13=5 12..8=0x1E +cm.mvsa01 c_sreg1 c_sreg2 1..0=2 15..13=5 12..10=3 6..5=1 +cm.mva01s c_sreg1 c_sreg2 1..0=2 15..13=5 12..10=3 6..5=3 diff --git a/extensions/rv_zcmt b/extensions/rv_zcmt new file mode 100644 index 0000000..fab3dc9 --- /dev/null +++ b/extensions/rv_zcmt @@ -0,0 +1 @@ +cm.jalt c_index 1..0=2 15..13=5 12..10=0 diff --git a/extensions/rv_zfbfmin b/extensions/rv_zfbfmin new file mode 100644 index 0000000..003c7b9 --- /dev/null +++ b/extensions/rv_zfbfmin @@ -0,0 +1,2 @@ +fcvt.bf16.s rd rs1 24..20=8 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.s.bf16 rd rs1 24..20=6 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 diff --git a/extensions/rv_zfh b/extensions/rv_zfh new file mode 100644 index 0000000..c2767fd --- /dev/null +++ b/extensions/rv_zfh @@ -0,0 +1,34 @@ +flh rd rs1 imm12 14..12=1 6..2=0x01 1..0=3 +fsh imm12hi rs1 rs2 imm12lo 14..12=1 6..2=0x09 1..0=3 +fmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x10 1..0=3 +fmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x11 1..0=3 +fnmsub.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x12 1..0=3 +fnmadd.h rd rs1 rs2 rs3 rm 26..25=2 6..2=0x13 1..0=3 +fadd.h rd rs1 rs2 31..27=0x00 rm 26..25=2 6..2=0x14 1..0=3 +fsub.h rd rs1 rs2 31..27=0x01 rm 26..25=2 6..2=0x14 1..0=3 +fmul.h rd rs1 rs2 31..27=0x02 rm 26..25=2 6..2=0x14 1..0=3 +fdiv.h rd rs1 rs2 31..27=0x03 rm 26..25=2 6..2=0x14 1..0=3 +fsqrt.h rd rs1 24..20=0 31..27=0x0B rm 26..25=2 6..2=0x14 1..0=3 +fsgnj.h rd rs1 rs2 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +fsgnjn.h rd rs1 rs2 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 +fsgnjx.h rd rs1 rs2 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmin.h rd rs1 rs2 31..27=0x05 14..12=0 26..25=2 6..2=0x14 1..0=3 +fmax.h rd rs1 rs2 31..27=0x05 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.s.h rd rs1 24..20=2 31..27=0x08 rm 26..25=0 6..2=0x14 1..0=3 +fcvt.h.s rd rs1 24..20=0 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 + +feq.h rd rs1 rs2 31..27=0x14 14..12=2 26..25=2 6..2=0x14 1..0=3 +flt.h rd rs1 rs2 31..27=0x14 14..12=1 26..25=2 6..2=0x14 1..0=3 +fle.h rd rs1 rs2 31..27=0x14 14..12=0 26..25=2 6..2=0x14 1..0=3 +fclass.h rd rs1 24..20=0 31..27=0x1C 14..12=1 26..25=2 6..2=0x14 1..0=3 +fcvt.w.h rd rs1 24..20=0 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.wu.h rd rs1 24..20=1 31..27=0x18 rm 26..25=2 6..2=0x14 1..0=3 +fmv.x.h rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=2 6..2=0x14 1..0=3 +fcvt.h.w rd rs1 24..20=0 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fcvt.h.wu rd rs1 24..20=1 31..27=0x1A rm 26..25=2 6..2=0x14 1..0=3 +fmv.h.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 + +#pseudoinstructions +$pseudo_op rv_zfh::fsgnj.h fmv.h rd rs1 rs2=rs1 31..27=0x04 14..12=0 26..25=2 6..2=0x14 1..0=3 +$pseudo_op rv_zfh::fsgnjx.h fabs.h rd rs1 rs2=rs1 31..27=0x04 14..12=2 26..25=2 6..2=0x14 1..0=3 +$pseudo_op rv_zfh::fsgnjn.h fneg.h rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=2 6..2=0x14 1..0=3 diff --git a/extensions/rv_zfh_zfa b/extensions/rv_zfh_zfa new file mode 100644 index 0000000..f92d7a9 --- /dev/null +++ b/extensions/rv_zfh_zfa @@ -0,0 +1,7 @@ +fli.h rd rs1 24..20=1 31..27=0x1E 14..12=0 26..25=2 6..2=0x14 1..0=3 +fminm.h rd rs1 rs2 31..27=0x05 14..12=2 26..25=2 6..2=0x14 1..0=3 +fmaxm.h rd rs1 rs2 31..27=0x05 14..12=3 26..25=2 6..2=0x14 1..0=3 +fround.h rd rs1 24..20=4 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +froundnx.h rd rs1 24..20=5 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fleq.h rd rs1 rs2 31..27=0x14 14..12=4 26..25=2 6..2=0x14 1..0=3 +fltq.h rd rs1 rs2 31..27=0x14 14..12=5 26..25=2 6..2=0x14 1..0=3 diff --git a/extensions/rv_zicbo b/extensions/rv_zicbo new file mode 100644 index 0000000..65a4567 --- /dev/null +++ b/extensions/rv_zicbo @@ -0,0 +1,12 @@ +# Zicbom: cache-block management instructions +cbo.clean rs1 31..20=1 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.flush rs1 31..20=2 14..12=2 11..7=0 6..2=0x03 1..0=3 +cbo.inval rs1 31..20=0 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicboz: cache-block zero instruction +cbo.zero rs1 31..20=4 14..12=2 11..7=0 6..2=0x03 1..0=3 + +# Zicbop: prefetch hint pseudoinstructions +$pseudo_op rv_i::ori prefetch.i rs1 imm12hi 24..20=0 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.r rs1 imm12hi 24..20=1 14..12=6 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::ori prefetch.w rs1 imm12hi 24..20=3 14..12=6 11..7=0 6..2=0x04 1..0=3 diff --git a/extensions/rv_zicfilp b/extensions/rv_zicfilp new file mode 100644 index 0000000..1ef4844 --- /dev/null +++ b/extensions/rv_zicfilp @@ -0,0 +1,2 @@ +# auipc x0 imm20 -> lpad imm20 +$pseudo_op rv_i::auipc lpad imm20 11..7=0 6..2=0x05 1..0=3 diff --git a/extensions/rv_zicfiss b/extensions/rv_zicfiss new file mode 100644 index 0000000..7e4fa47 --- /dev/null +++ b/extensions/rv_zicfiss @@ -0,0 +1,13 @@ +ssamoswap.w rd rs1 rs2 aq rl 31..29=2 28..27=1 14..12=2 6..2=0x0B 1..0=3 +ssamoswap.d rd rs1 rs2 aq rl 31..29=2 28..27=1 14..12=3 6..2=0x0B 1..0=3 + +# sspopchk x1/x5 -> mop.r.28 rd=x0, rs1=x1/x5 +$pseudo_op rv_zimop::mop.r.N sspopchk.x1 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=1 14..12=4 11..7=0 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N sspopchk.x5 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=5 14..12=4 11..7=0 6..2=0x1C 1..0=3 + +# ssrdp rd != x0 -> mop.r.28 rd!=x0, rs1=x0 +$pseudo_op rv_zimop::mop.r.N ssrdp rd_n0 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 19..15=0 14..12=4 6..2=0x1C 1..0=3 + +# sspush x1/x5 -> mop.rr.7 rd=x0, rs2=x1/x5, rs1=x0 +$pseudo_op rv_zimop::mop.rr.N sspush.x1 30=1 27=1 26=1 31=1 29..28=0 25=1 24..20=1 19..15=0 14..12=4 11..7=0 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N sspush.x5 30=1 27=1 26=1 31=1 29..28=0 25=1 24..20=5 19..15=0 14..12=4 11..7=0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_zicntr b/extensions/rv_zicntr new file mode 100644 index 0000000..bedae43 --- /dev/null +++ b/extensions/rv_zicntr @@ -0,0 +1,4 @@ +#rv_zicntr instructions
+$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
diff --git a/extensions/rv_zicond b/extensions/rv_zicond new file mode 100644 index 0000000..1676f05 --- /dev/null +++ b/extensions/rv_zicond @@ -0,0 +1,2 @@ +czero.eqz rd rs1 rs2 31..25=7 14..12=5 6..2=0x0C 1..0=3 +czero.nez rd rs1 rs2 31..25=7 14..12=7 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zicsr b/extensions/rv_zicsr new file mode 100644 index 0000000..9541556 --- /dev/null +++ b/extensions/rv_zicsr @@ -0,0 +1,15 @@ +csrrw rd rs1 csr 14..12=1 6..2=0x1C 1..0=3 +csrrs rd rs1 csr 14..12=2 6..2=0x1C 1..0=3 +csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 +csrrwi rd csr zimm5 14..12=5 6..2=0x1C 1..0=3 +csrrsi rd csr zimm5 14..12=6 6..2=0x1C 1..0=3 +csrrci rd csr zimm5 14..12=7 6..2=0x1C 1..0=3 + +#pseudoinstructions +$pseudo_op rv_zicsr::csrrs csrr rd csr 19..15=0x0 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw csrw rs1 csr 14..12=1 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs csrs rs1 csr 14..12=2 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrc csrc rs1 csr 14..12=3 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi csrwi csr zimm5 14..12=5 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrsi csrsi csr zimm5 14..12=6 11..7=0x0 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrci csrci csr zimm5 14..12=7 11..7=0x0 6..2=0x1C 1..0=3 diff --git a/extensions/rv_zifencei b/extensions/rv_zifencei new file mode 100644 index 0000000..5f6fd7e --- /dev/null +++ b/extensions/rv_zifencei @@ -0,0 +1 @@ +fence.i imm12 rs1 14..12=1 rd 6..2=0x03 1..0=3 diff --git a/extensions/rv_zihintntl b/extensions/rv_zihintntl new file mode 100644 index 0000000..56de9ea --- /dev/null +++ b/extensions/rv_zihintntl @@ -0,0 +1,4 @@ +$pseudo_op rv_i::add ntl.p1 31..25=0 24..20=2 19..15=0 14..12=0 11..7=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::add ntl.pall 31..25=0 24..20=3 19..15=0 14..12=0 11..7=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::add ntl.s1 31..25=0 24..20=4 19..15=0 14..12=0 11..7=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::add ntl.all 31..25=0 24..20=5 19..15=0 14..12=0 11..7=0 6..2=0x0C 1..0=3 diff --git a/extensions/rv_zimop b/extensions/rv_zimop new file mode 100644 index 0000000..c1dcea0 --- /dev/null +++ b/extensions/rv_zimop @@ -0,0 +1,53 @@ +# The Zimop extension defines 32 MOP instructions named mop.r.0 -- mop.r.31. +# They are encoded as 1-00--0111--sssss100ddddd1110011, where - denotes an +# available opcode bit, s denotes the rs1 field, and d denotes the rd field. +# add a pseudo-inst mop.r.N that matches mop.r.* + +mop.r.N mop_r_t_30 mop_r_t_27_26 mop_r_t_21_20 rd rs1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.0 rd rs1 30=0 27=0 26=0 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.1 rd rs1 30=0 27=0 26=0 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.2 rd rs1 30=0 27=0 26=0 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.3 rd rs1 30=0 27=0 26=0 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.4 rd rs1 30=0 27=0 26=1 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.5 rd rs1 30=0 27=0 26=1 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.6 rd rs1 30=0 27=0 26=1 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.7 rd rs1 30=0 27=0 26=1 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.8 rd rs1 30=0 27=1 26=0 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.9 rd rs1 30=0 27=1 26=0 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.10 rd rs1 30=0 27=1 26=0 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.11 rd rs1 30=0 27=1 26=0 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.12 rd rs1 30=0 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.13 rd rs1 30=0 27=1 26=1 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.14 rd rs1 30=0 27=1 26=1 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.15 rd rs1 30=0 27=1 26=1 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.16 rd rs1 30=1 27=0 26=0 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.17 rd rs1 30=1 27=0 26=0 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.18 rd rs1 30=1 27=0 26=0 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.19 rd rs1 30=1 27=0 26=0 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.20 rd rs1 30=1 27=0 26=1 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.21 rd rs1 30=1 27=0 26=1 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.22 rd rs1 30=1 27=0 26=1 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.23 rd rs1 30=1 27=0 26=1 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.24 rd rs1 30=1 27=1 26=0 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.25 rd rs1 30=1 27=1 26=0 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.26 rd rs1 30=1 27=1 26=0 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.27 rd rs1 30=1 27=1 26=0 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.28 rd rs1 30=1 27=1 26=1 21=0 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.29 rd rs1 30=1 27=1 26=1 21=0 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.30 rd rs1 30=1 27=1 26=1 21=1 20=0 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.r.N mop.r.31 rd rs1 30=1 27=1 26=1 21=1 20=1 31=1 29..28=0 25..22=7 14..12=4 6..2=0x1C 1..0=3 + +# The Zimop extension additionally defines 8 MOP instructions named mop.rr.0 +# -- mop.rr.7. They are encoded as 1-00--1tttttsssss100ddddd1110011, where t +# denotes the rs2 field. +# add a pseudo-inst mop.rr.N taht matches mop.rr.* + +mop.rr.N mop_rr_t_30 mop_rr_t_27_26 rd rs1 rs2 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.0 rd rs1 rs2 30=0 27=0 26=0 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.1 rd rs1 rs2 30=0 27=0 26=1 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.2 rd rs1 rs2 30=0 27=1 26=0 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.3 rd rs1 rs2 30=0 27=1 26=1 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.4 rd rs1 rs2 30=1 27=0 26=0 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.5 rd rs1 rs2 30=1 27=0 26=1 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.6 rd rs1 rs2 30=1 27=1 26=0 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 +$pseudo_op rv_zimop::mop.rr.N mop.rr.7 rd rs1 rs2 30=1 27=1 26=1 31=1 29..28=0 25=1 14..12=4 6..2=0x1C 1..0=3 diff --git a/extensions/rv_zk b/extensions/rv_zk new file mode 100644 index 0000000..dc60ee5 --- /dev/null +++ b/extensions/rv_zk @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbkb::pack +$import rv_zbkb::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/extensions/rv_zkn b/extensions/rv_zkn new file mode 100644 index 0000000..dc60ee5 --- /dev/null +++ b/extensions/rv_zkn @@ -0,0 +1,24 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbkb::pack +$import rv_zbkb::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +#import zknh +# Scalar SHA256 - RV32/RV64 +$import rv_zknh::sha256sum0 +$import rv_zknh::sha256sum1 +$import rv_zknh::sha256sig0 +$import rv_zknh::sha256sig1 diff --git a/extensions/rv_zknh b/extensions/rv_zknh new file mode 100644 index 0000000..2079628 --- /dev/null +++ b/extensions/rv_zknh @@ -0,0 +1,5 @@ +# Scalar SHA256 - RV32/RV64 +sha256sum0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00000 14..12=1 6..0=0x13 +sha256sum1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00001 14..12=1 6..0=0x13 +sha256sig0 rd rs1 31..30=0 29..25=0b01000 24..20=0b00010 14..12=1 6..0=0x13 +sha256sig1 rd rs1 31..30=0 29..25=0b01000 24..20=0b00011 14..12=1 6..0=0x13 diff --git a/extensions/rv_zks b/extensions/rv_zks new file mode 100644 index 0000000..c78c215 --- /dev/null +++ b/extensions/rv_zks @@ -0,0 +1,25 @@ +# import zbkb +$import rv_zbb::rol +$import rv_zbb::ror +$import rv_zbb::andn +$import rv_zbb::orn +$import rv_zbb::xnor +$import rv_zbkb::pack +$import rv_zbkb::packh +$pseudo_op rv64_zbp::grevi brev8 rd rs1 31..20=0x687 14..12=5 6..2=0x4 1..0=0x3 + +#import zbkc +$import rv_zbc::clmul +$import rv_zbc::clmulh + +#import zbkx +$import rv_zbkx::xperm4 +$import rv_zbkx::xperm8 + +# Scalar SM4 - RV32, RV64 +$import rv_zksed::sm4ed +$import rv_zksed::sm4ks + +# Scalar SM3 - RV32, RV64 +$import rv_zksh::sm3p0 +$import rv_zksh::sm3p1 diff --git a/extensions/rv_zksed b/extensions/rv_zksed new file mode 100644 index 0000000..7975b5d --- /dev/null +++ b/extensions/rv_zksed @@ -0,0 +1,3 @@ +# Scalar SM4 - RV32, RV64 +sm4ed rd rs1 rs2 bs 29..25=0b11000 14..12=0 6..0=0x33 +sm4ks rd rs1 rs2 bs 29..25=0b11010 14..12=0 6..0=0x33 diff --git a/extensions/rv_zksh b/extensions/rv_zksh new file mode 100644 index 0000000..24e5f70 --- /dev/null +++ b/extensions/rv_zksh @@ -0,0 +1,3 @@ +# Scalar SM3 - RV32, RV64 +sm3p0 rd rs1 31..30=0 29..25=0b01000 24..20=0b01000 14..12=1 6..0=0x13 +sm3p1 rd rs1 31..30=0 29..25=0b01000 24..20=0b01001 14..12=1 6..0=0x13 diff --git a/extensions/rv_zvbb b/extensions/rv_zvbb new file mode 100644 index 0000000..dc48ee2 --- /dev/null +++ b/extensions/rv_zvbb @@ -0,0 +1,37 @@ +# Zvbb - Vector Bit-manipulation used in Cryptography + +# Vector And-Not +vandn.vv 31..26=0x01 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vandn.vx 31..26=0x01 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +# Vector Reverse Bits in Elements +vbrev.v 31..26=0x12 vm vs2 19..15=0xA 14..12=0x2 vd 6..0=0x57 + +# Vector Reverse Bits in Bytes +vbrev8.v 31..26=0x12 vm vs2 19..15=0x8 14..12=0x2 vd 6..0=0x57 + +# Vector Reverse Bytes +vrev8.v 31..26=0x12 vm vs2 19..15=0x9 14..12=0x2 vd 6..0=0x57 + +# Vector Count Leading Zeros +vclz.v 31..26=0x12 vm vs2 19..15=0xC 14..12=0x2 vd 6..0=0x57 + +# Vector Count Trailing Zeros +vctz.v 31..26=0x12 vm vs2 19..15=0xD 14..12=0x2 vd 6..0=0x57 + +# Vector Population Count +vcpop.v 31..26=0x12 vm vs2 19..15=0xE 14..12=0x2 vd 6..0=0x57 + +# Vector Rotate Left +vrol.vv 31..26=0x15 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vrol.vx 31..26=0x15 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 + +# Vector Rotate Right +vror.vv 31..26=0x14 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vror.vx 31..26=0x14 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vror.vi 31..27=0xa zimm6hi vm vs2 zimm6lo 14..12=0x3 vd 6..0=0x57 + +# Vector Widening Shift Left Logical +vwsll.vv 31..26=0x35 vm vs2 vs1 14..12=0x0 vd 6..0=0x57 +vwsll.vx 31..26=0x35 vm vs2 rs1 14..12=0x4 vd 6..0=0x57 +vwsll.vi 31..26=0x35 vm vs2 zimm5 14..12=0x3 vd 6..0=0x57 diff --git a/extensions/rv_zvbc b/extensions/rv_zvbc new file mode 100644 index 0000000..95bf431 --- /dev/null +++ b/extensions/rv_zvbc @@ -0,0 +1,9 @@ +# Zvbc - Vector Carryless Multiplication + +# Carryless Multiply +vclmul.vv 31..26=0x0C vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vclmul.vx 31..26=0x0C vm vs2 rs1 14..12=0x6 vd 6..0=0x57 + +# Carryless Multiply (High) +vclmulh.vv 31..26=0x0D vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vclmulh.vx 31..26=0x0D vm vs2 rs1 14..12=0x6 vd 6..0=0x57 diff --git a/extensions/rv_zvfbfmin b/extensions/rv_zvfbfmin new file mode 100644 index 0000000..8908959 --- /dev/null +++ b/extensions/rv_zvfbfmin @@ -0,0 +1,2 @@ +vfncvtbf16.f.f.w 31..26=0x12 vm vs2 19..15=0x1D 14..12=0x1 vd 6..0=0x57 +vfwcvtbf16.f.f.v 31..26=0x12 vm vs2 19..15=0x0D 14..12=0x1 vd 6..0=0x57 diff --git a/extensions/rv_zvfbfwma b/extensions/rv_zvfbfwma new file mode 100644 index 0000000..27b4ae6 --- /dev/null +++ b/extensions/rv_zvfbfwma @@ -0,0 +1,2 @@ +vfwmaccbf16.vv 31..26=0x3B vm vs2 vs1 14..12=0x1 vd 6..0=0x57 +vfwmaccbf16.vf 31..26=0x3B vm vs2 rs1 14..12=0x5 vd 6..0=0x57 diff --git a/extensions/rv_zvkg b/extensions/rv_zvkg new file mode 100644 index 0000000..0b99b5b --- /dev/null +++ b/extensions/rv_zvkg @@ -0,0 +1,7 @@ +# Zvkg - Vector GCM/GMAC + +# Vector Multiply over GHASH Galois-Field +vgmul.vv 31..26=0x28 25=1 vs2 19..15=0x11 14..12=0x2 vd 6..0=0x77 + +# Vector Add-Multiply over GHASH Galois-Field +vghsh.vv 31..26=0x2C 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77 diff --git a/extensions/rv_zvkn b/extensions/rv_zvkn new file mode 100644 index 0000000..5a17e6d --- /dev/null +++ b/extensions/rv_zvkn @@ -0,0 +1,46 @@ +# Zvkn, Vector Crypto Extension, NIST Algorithm Suite + +# Import Zvbb +$import rv_zvbb::vandn.vv +$import rv_zvbb::vandn.vx +$import rv_zvbb::vbrev.v +$import rv_zvbb::vbrev8.v +$import rv_zvbb::vrev8.v +$import rv_zvbb::vrol.vv +$import rv_zvbb::vrol.vx +$import rv_zvbb::vror.vv +$import rv_zvbb::vror.vx +$import rv_zvbb::vror.vi +$import rv_zvbb::vclz.v +$import rv_zvbb::vctz.v +$import rv_zvbb::vcpop.v +$import rv_zvbb::vwsll.vv +$import rv_zvbb::vwsll.vx +$import rv_zvbb::vwsll.vi + +# Import Zvbc +$import rv_zvbc::vclmul.vv +$import rv_zvbc::vclmul.vx +$import rv_zvbc::vclmulh.vv +$import rv_zvbc::vclmulh.vx + +# Import Zvkned +$import rv_zvkned::vaesef.vs +$import rv_zvkned::vaesef.vv +$import rv_zvkned::vaesem.vs +$import rv_zvkned::vaesem.vv +$import rv_zvkned::vaesdf.vs +$import rv_zvkned::vaesdf.vv +$import rv_zvkned::vaesdm.vs +$import rv_zvkned::vaesdm.vv +$import rv_zvkned::vaeskf1.vi +$import rv_zvkned::vaeskf2.vi +$import rv_zvkned::vaesz.vs + +# Import Zvknh. +# "Zvkn" implies "Zvknhb". We import the instructions from 'rv_zvknha', +# because we cannot import already imported instructions, 'rv_zvknhb' +# imports them from 'rv_zvknha', and the instructions are identical. +$import rv_zvknha::vsha2ms.vv +$import rv_zvknha::vsha2ch.vv +$import rv_zvknha::vsha2cl.vv diff --git a/extensions/rv_zvkned b/extensions/rv_zvkned new file mode 100644 index 0000000..572b465 --- /dev/null +++ b/extensions/rv_zvkned @@ -0,0 +1,21 @@ +# Zvkned - Vector Crypto AES Encryption & Decryption (Singe Round) + +# AES Single Round Decryption +vaesdf.vv 31..26=0x28 25=1 vs2 19..15=0x1 14..12=0x2 vd 6..0=0x77 +vaesdf.vs 31..26=0x29 25=1 vs2 19..15=0x1 14..12=0x2 vd 6..0=0x77 +vaesdm.vv 31..26=0x28 25=1 vs2 19..15=0x0 14..12=0x2 vd 6..0=0x77 +vaesdm.vs 31..26=0x29 25=1 vs2 19..15=0x0 14..12=0x2 vd 6..0=0x77 + +# AES Single Round Encryption +vaesef.vv 31..26=0x28 25=1 vs2 19..15=0x3 14..12=0x2 vd 6..0=0x77 +vaesef.vs 31..26=0x29 25=1 vs2 19..15=0x3 14..12=0x2 vd 6..0=0x77 +vaesem.vv 31..26=0x28 25=1 vs2 19..15=0x2 14..12=0x2 vd 6..0=0x77 +vaesem.vs 31..26=0x29 25=1 vs2 19..15=0x2 14..12=0x2 vd 6..0=0x77 + +# AES Scalar Round Zero Encryption/Decryption +vaesz.vs 31..26=0x29 25=1 vs2 19..15=0x7 14..12=0x2 vd 6..0=0x77 + +# AES-128 Forward Key Schedule +vaeskf1.vi 31..26=0x22 25=1 vs2 zimm5 14..12=0x2 vd 6..0=0x77 +# AES-256 Forward Key Schedule +vaeskf2.vi 31..26=0x2A 25=1 vs2 zimm5 14..12=0x2 vd 6..0=0x77 diff --git a/extensions/rv_zvknha b/extensions/rv_zvknha new file mode 100644 index 0000000..a09a36c --- /dev/null +++ b/extensions/rv_zvknha @@ -0,0 +1,9 @@ +# Zvknha - Vector Crypto SHA-256 Secure Hash +# +# The following 3 instructions are defined in both Zvknha and Zvknhb: +# - in Zvknha, they support SHA-256 (SEW=32) only, +# - in Zvknhb, they support both SHA-256 (SEW=32) and SHA-512 (SEW=64). + +vsha2ms.vv 31..26=0x2D 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77 +vsha2ch.vv 31..26=0x2E 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77 +vsha2cl.vv 31..26=0x2F 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77 diff --git a/extensions/rv_zvknhb b/extensions/rv_zvknhb new file mode 100644 index 0000000..c0b0d8f --- /dev/null +++ b/extensions/rv_zvknhb @@ -0,0 +1,9 @@ +# Zvknhb - Vector Crypto SHA-256 and SHA-512 Secure Hash +# +# The following 3 instructions are defined in both Zvknha and Zvknhb: +# - in Zvknha, they support SHA-256 (SEW=32) only, +# - in Zvknhb, they support both SHA-256 (SEW=32) and SHA-512 (SEW=64). + +$import rv_zvknha::vsha2ms.vv +$import rv_zvknha::vsha2ch.vv +$import rv_zvknha::vsha2cl.vv diff --git a/extensions/rv_zvks b/extensions/rv_zvks new file mode 100644 index 0000000..b5448bf --- /dev/null +++ b/extensions/rv_zvks @@ -0,0 +1,34 @@ +# Zvk, Vector Crypto Extension, ShangMi Algorithm Suite + +# Import Zvbb +$import rv_zvbb::vandn.vv +$import rv_zvbb::vandn.vx +$import rv_zvbb::vbrev.v +$import rv_zvbb::vbrev8.v +$import rv_zvbb::vrev8.v +$import rv_zvbb::vrol.vv +$import rv_zvbb::vrol.vx +$import rv_zvbb::vror.vv +$import rv_zvbb::vror.vx +$import rv_zvbb::vror.vi +$import rv_zvbb::vclz.v +$import rv_zvbb::vctz.v +$import rv_zvbb::vcpop.v +$import rv_zvbb::vwsll.vv +$import rv_zvbb::vwsll.vx +$import rv_zvbb::vwsll.vi + +# Import Zvbc +$import rv_zvbc::vclmul.vv +$import rv_zvbc::vclmul.vx +$import rv_zvbc::vclmulh.vv +$import rv_zvbc::vclmulh.vx + +# Import Zvksed +$import rv_zvksed::vsm4k.vi +$import rv_zvksed::vsm4r.vv +$import rv_zvksed::vsm4r.vs + +# Import Zvksh +$import rv_zvksh::vsm3c.vi +$import rv_zvksh::vsm3me.vv diff --git a/extensions/rv_zvksed b/extensions/rv_zvksed new file mode 100644 index 0000000..b0b3037 --- /dev/null +++ b/extensions/rv_zvksed @@ -0,0 +1,8 @@ +# Zvksed - Vector Crypto SM4 (Block Cipher) + +# SM4 Key Expansion +vsm4k.vi 31..26=0x21 25=1 vs2 zimm5 14..12=0x2 vd 6..0=0x77 + +# SM4 Encryption/Decryption Rounds +vsm4r.vv 31..26=0x28 25=1 vs2 19..15=0x10 14..12=0x2 vd 6..0=0x77 +vsm4r.vs 31..26=0x29 25=1 vs2 19..15=0x10 14..12=0x2 vd 6..0=0x77 diff --git a/extensions/rv_zvksh b/extensions/rv_zvksh new file mode 100644 index 0000000..2dc6f6c --- /dev/null +++ b/extensions/rv_zvksh @@ -0,0 +1,7 @@ +# Zvksh - Vector Crypto SM3 (Hash) + +# SM3 Message Compression +vsm3c.vi 31..26=0x2B 25=1 vs2 zimm5 14..12=0x2 vd 6..0=0x77 + +# SM3 Message Expansion +vsm3me.vv 31..26=0x20 25=1 vs2 vs1 14..12=0x2 vd 6..0=0x77 diff --git a/extensions/unratified/rv64_zbp b/extensions/unratified/rv64_zbp new file mode 100644 index 0000000..98d0b2e --- /dev/null +++ b/extensions/unratified/rv64_zbp @@ -0,0 +1,5 @@ +grevi rd rs1 31..26=26 shamtd 14..12=5 6..2=0x04 1..0=3 +gorci rd rs1 31..26=10 shamtd 14..12=5 6..2=0x04 1..0=3 +shfli rd rs1 31..26=2 25=0 shamtw 14..12=1 6..2=0x04 1..0=3 +unshfli rd rs1 31..26=2 25=0 shamtw 14..12=5 6..2=0x04 1..0=3 +xperm32 rd rs1 rs2 31..25=20 14..12=0 6..2=0x0C 1..0=3 diff --git a/extensions/unratified/rv_zalasr b/extensions/unratified/rv_zalasr new file mode 100644 index 0000000..43af470 --- /dev/null +++ b/extensions/unratified/rv_zalasr @@ -0,0 +1,8 @@ +lb.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=0 6..2=0x0B 1..0=3 +lh.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=1 6..2=0x0B 1..0=3 +lw.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=2 6..2=0x0B 1..0=3 +ld.aq rd rs1 26=1 rl 31..27=6 24..20=0 14..12=3 6..2=0x0B 1..0=3 +sb.rl rs1 rs2 aq 25=1 31..27=7 14..12=0 11..7=0 6..2=0x0B 1..0=3 +sh.rl rs1 rs2 aq 25=1 31..27=7 14..12=1 11..7=0 6..2=0x0B 1..0=3 +sw.rl rs1 rs2 aq 25=1 31..27=7 14..12=2 11..7=0 6..2=0x0B 1..0=3 +sd.rl rs1 rs2 aq 25=1 31..27=7 14..12=3 11..7=0 6..2=0x0B 1..0=3 diff --git a/extensions/unratified/rv_zbp b/extensions/unratified/rv_zbp new file mode 100644 index 0000000..bd95dd2 --- /dev/null +++ b/extensions/unratified/rv_zbp @@ -0,0 +1 @@ +xperm16 rd rs1 rs2 31..25=20 14..12=6 6..2=0x0C 1..0=3 diff --git a/extensions/unratified/rv_zvfofp8min b/extensions/unratified/rv_zvfofp8min new file mode 100644 index 0000000..5ea7959 --- /dev/null +++ b/extensions/unratified/rv_zvfofp8min @@ -0,0 +1,3 @@ +vfncvtbf16.f.f.q 31..26=0x12 vm vs2 19..15=0x19 14..12=0x1 vd 6..0=0x57 +vfncvtbf16.sat.f.f.q 31..26=0x12 vm vs2 19..15=0x1B 14..12=0x1 vd 6..0=0x57 +vfncvtbf16.sat.f.f.w 31..26=0x12 vm vs2 19..15=0x1F 14..12=0x1 vd 6..0=0x57 diff --git a/extensions/unratified/rv_zvqdotq b/extensions/unratified/rv_zvqdotq new file mode 100644 index 0000000..94782e4 --- /dev/null +++ b/extensions/unratified/rv_zvqdotq @@ -0,0 +1,7 @@ +vqdot.vv 31..26=0x2c vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vqdot.vx 31..26=0x2c vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vqdotu.vv 31..26=0x28 vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vqdotu.vx 31..26=0x28 vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vqdotsu.vv 31..26=0x2a vm vs2 vs1 14..12=0x2 vd 6..0=0x57 +vqdotsu.vx 31..26=0x2a vm vs2 rs1 14..12=0x6 vd 6..0=0x57 +vqdotus.vx 31..26=0x2e vm vs2 rs1 14..12=0x6 vd 6..0=0x57 |