diff options
| -rwxr-xr-x | parse.py | 42 | ||||
| -rw-r--r-- | rv32_zicntr | 4 | ||||
| -rw-r--r-- | rv64_i | 2 | ||||
| -rw-r--r-- | rv_f | 9 | ||||
| -rw-r--r-- | rv_i | 25 | ||||
| -rw-r--r-- | rv_zicntr | 5 | ||||
| -rw-r--r-- | rv_zicsr | 17 |
7 files changed, 86 insertions, 18 deletions
@@ -1,6 +1,7 @@ #!/usr/bin/env python3 from constants import * +import copy import re import glob import os @@ -164,6 +165,37 @@ def extension_overlap_allowed(x, y): def instruction_overlap_allowed(x, y): return overlap_allowed(overlapping_instructions, x, y) +def add_segmented_vls_insn(instr_dict): + updated_dict = {} + for k, v in instr_dict.items(): + if "nf" in v['variable_fields']: + for new_key, new_value in expand_nf_field(k,v): + updated_dict[new_key] = new_value + else: + updated_dict[k] = v + return updated_dict + +def expand_nf_field(name, single_dict): + if "nf" not in single_dict['variable_fields']: + logging.error(f"Cannot expand nf field for instruction {name}") + raise SystemExit(1) + + # nf no longer a variable field + single_dict['variable_fields'].remove("nf") + # include nf in mask + single_dict['mask'] = hex(int(single_dict['mask'],16) | 0b111 << 29) + + name_expand_index = name.find('e') + expanded_instructions = [] + for nf in range(0,8): + new_single_dict = copy.deepcopy(single_dict) + new_single_dict['match'] = hex(int(single_dict['match'],16) | nf << 29) + new_single_dict['encoding'] = format(nf, '03b') + single_dict['encoding'][3:] + new_name = name if nf == 0 else name[:name_expand_index] + "seg" + str(nf+1) + name[name_expand_index:] + expanded_instructions.append((new_name, new_single_dict)) + return expanded_instructions + + def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): ''' This function return a dictionary containing all instructions associated @@ -336,6 +368,13 @@ def create_inst_dict(file_filter, include_pseudo=False, include_pseudo_ops=[]): if name not in instr_dict: instr_dict[name] = single_dict logging.debug(f' including pseudo_ops:{name}') + else: + # if a pseudo instruction has already been added to the filtered + # instruction dictionary but the extension is not in the current + # list, add it + ext_name = single_dict['extension'] + if ext_name not in instr_dict[name]['extension']: + instr_dict[name]['extension'].extend(ext_name) else: logging.debug(f' Skipping pseudo_op {pseudo_inst} since original instruction {orig_inst} already selected in list') @@ -1001,8 +1040,9 @@ if __name__ == "__main__": include_pseudo = True instr_dict = create_inst_dict(extensions, include_pseudo) + with open('instr_dict.yaml', 'w') as outfile: - yaml.dump(instr_dict, outfile, default_flow_style=False) + yaml.dump(add_segmented_vls_insn(instr_dict), outfile, default_flow_style=False) instr_dict = collections.OrderedDict(sorted(instr_dict.items())) if '-c' in sys.argv[1:]: diff --git a/rv32_zicntr b/rv32_zicntr new file mode 100644 index 0000000..2744bb2 --- /dev/null +++ b/rv32_zicntr @@ -0,0 +1,4 @@ +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
+
@@ -18,3 +18,5 @@ subw rd rs1 rs2 31..25=32 14..12=0 6..2=0x0E 1..0=3 sllw rd rs1 rs2 31..25=0 14..12=1 6..2=0x0E 1..0=3 srlw rd rs1 rs2 31..25=0 14..12=5 6..2=0x0E 1..0=3 sraw rd rs1 rs2 31..25=32 14..12=5 6..2=0x0E 1..0=3 + +$pseudo_op rv64_i::addiw sext.w rd rs1 31..20=0 14..12=0 6..2=0x06 1..0=3
\ No newline at end of file @@ -29,3 +29,12 @@ fmv.w.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.x.w fmv.x.s rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=0 6..2=0x14 1..0=3 $pseudo_op rv_f::fmv.w.x fmv.s.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=0 6..2=0x14 1..0=3 +#CSRs +$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 +$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 @@ -45,3 +45,28 @@ ebreak 31..20=0x001 19..7=0 6..2=0x1C 1..0=3 $pseudo_op rv_i::ecall scall 11..7=0 19..15=0 31..20=0x000 14..12=0 6..2=0x1C 1..0=3 $pseudo_op rv_i::ebreak sbreak 11..7=0 19..15=0 31..20=0x001 14..12=0 6..2=0x1C 1..0=3 + +#pseudoinstructions from asm manual +$pseudo_op rv_i::addi mv rd rs1 31..20=0 14..12=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::sub neg rd rs1 31..25=32 24..20=0x0 14..12=0 6..2=0x0C 1..0=3 +$pseudo_op rv_i::addi nop 31..20=0 19..15=0 14..12=0 11..7=0 6..2=0x04 1..0=3 +$pseudo_op rv_i::andi zext.b rd rs1 31..20=0 14..12=7 6..2=0x04 1..0=3 + +$pseudo_op rv_i::jalr ret 31..20=0 19..15=0x01 14..12=0 11..7=0 6..2=0x19 1..0=3 + +$pseudo_op rv_i::bgeu bleu bimm12hi rs2 rs1 bimm12lo 14..12=7 6..2=0x18 1..0=3 +$pseudo_op rv_i::bltu bgtu bimm12hi rs2 rs1 bimm12lo 14..12=6 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge ble bimm12hi rs2 rs1 bimm12lo 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge bgez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::bge blez bimm12hi rs2 bimm12lo 19..15=0x0 14..12=5 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgt bimm12hi rs2 rs1 bimm12lo 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bgtz bimm12hi rs2 bimm12lo 19..15=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::blt bltz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=4 6..2=0x18 1..0=3 +$pseudo_op rv_i::bne bnez bimm12hi rs1 bimm12lo 24..20=0x0 14..12=1 6..2=0x18 1..0=3 +$pseudo_op rv_i::beq beqz bimm12hi rs1 bimm12lo 24..20=0x0 14..12=0 6..2=0x18 1..0=3 + +$pseudo_op rv_i::sltiu seqz rd rs1 31..20=1 14..12=3 6..2=0x04 1..0=3 +$pseudo_op rv_i::sltu snez rd rs2 31..25=0 19..15=0x0 14..12=3 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sltz rd rs1 31..25=0 24..20=0x0 14..12=2 6..2=0x0C 1..0=3 +$pseudo_op rv_i::slt sgtz rd rs2 31..25=0 19..15=0x0 14..12=2 6..2=0x0C 1..0=3 + diff --git a/rv_zicntr b/rv_zicntr new file mode 100644 index 0000000..deecaa0 --- /dev/null +++ b/rv_zicntr @@ -0,0 +1,5 @@ +#rv_zicntr instructions
+$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
+
@@ -4,20 +4,3 @@ csrrc rd rs1 csr 14..12=3 6..2=0x1C 1..0=3 csrrwi rd csr zimm 14..12=5 6..2=0x1C 1..0=3 csrrsi rd csr zimm 14..12=6 6..2=0x1C 1..0=3 csrrci rd csr zimm 14..12=7 6..2=0x1C 1..0=3 - -$pseudo_op rv_zicsr::csrrs frflags rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsflags rd rs1 31..20=0x001 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsflagsi rd zimm 31..20=0x001 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frrm rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 - - |