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| author | Tim Hutt <tdhutt@gmail.com> | 2024-10-29 21:11:51 +0000 |
|---|---|---|
| committer | Tim Hutt <timothy.hutt@codasip.com> | 2024-10-29 21:11:51 +0000 |
| commit | 938e6d5b038426cf881e433040b16803d82288a3 (patch) | |
| tree | 7c61446754b331bb761da7d29f440fff78568d01 /sverilog_utils.py | |
| parent | aa5687996a82e1b1aa32dcba537dd263b5af9f55 (diff) | |
| download | riscv-opcodes-938e6d5b038426cf881e433040b16803d82288a3.zip riscv-opcodes-938e6d5b038426cf881e433040b16803d82288a3.tar.gz riscv-opcodes-938e6d5b038426cf881e433040b16803d82288a3.tar.bz2 | |
Remove unused imports
Remove unused Python import statements.
Diffstat (limited to 'sverilog_utils.py')
| -rw-r--r-- | sverilog_utils.py | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/sverilog_utils.py b/sverilog_utils.py index 1fe2068..8916313 100644 --- a/sverilog_utils.py +++ b/sverilog_utils.py @@ -1,12 +1,5 @@ -import collections -import glob import logging -import os import pprint -import re -import sys - -import yaml # from shared_utils import overlaps, overlap_allowed, extension_overlap_allowed, instruction_overlap_allowed, process_enc_line, same_base_isa, add_segmented_vls_insn, expand_nf_field from shared_utils import * |