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| author | Andrew Waterman <andrew@sifive.com> | 2024-10-28 14:42:32 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-28 14:42:32 -0700 |
| commit | 238c183f04551a29d18afe97942873cf1f03af11 (patch) | |
| tree | 48e6ccb685a944b2c78963d4b9006caec24f1470 /sverilog_utils.py | |
| parent | 25c09e69c72371d1f72ff22c3359e83a4b3247a7 (diff) | |
| parent | 83b56f6ce605f06dd605f43d36729dc89f92bd07 (diff) | |
| download | riscv-opcodes-238c183f04551a29d18afe97942873cf1f03af11.zip riscv-opcodes-238c183f04551a29d18afe97942873cf1f03af11.tar.gz riscv-opcodes-238c183f04551a29d18afe97942873cf1f03af11.tar.bz2 | |
Merge pull request #307 from foss-for-synopsys-dwc-arc-processors/includePseudo
Added make option to include Pseudo
Diffstat (limited to 'sverilog_utils.py')
0 files changed, 0 insertions, 0 deletions