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author | IIITM-Jay <jaydev.neuroscitech@gmail.com> | 2024-09-17 00:53:00 +0530 |
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committer | IIITM-Jay <jaydev.neuroscitech@gmail.com> | 2024-09-17 00:53:00 +0530 |
commit | 1b0ef5d896a1652dc52a5353521d9990d481c76b (patch) | |
tree | dc18afacd59344a65a690093b1b4e8e4f278c6f6 /sverilog_utils.py | |
parent | 6a1be96c8238d603a50d956ff1f91defa264785b (diff) | |
download | riscv-opcodes-1b0ef5d896a1652dc52a5353521d9990d481c76b.zip riscv-opcodes-1b0ef5d896a1652dc52a5353521d9990d481c76b.tar.gz riscv-opcodes-1b0ef5d896a1652dc52a5353521d9990d481c76b.tar.bz2 |
Refactored and Optimized Logic:: Parser Logic, Latex Based Output & Shared Modules
Diffstat (limited to 'sverilog_utils.py')
-rw-r--r-- | sverilog_utils.py | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/sverilog_utils.py b/sverilog_utils.py new file mode 100644 index 0000000..4a6ace1 --- /dev/null +++ b/sverilog_utils.py @@ -0,0 +1,30 @@ +import re +import glob +import os +import pprint +import logging +import collections +import yaml +import sys +# from shared_utils import overlaps, overlap_allowed, extension_overlap_allowed, instruction_overlap_allowed, process_enc_line, same_base_isa, add_segmented_vls_insn, expand_nf_field +from shared_utils import * + +pp = pprint.PrettyPrinter(indent=2) +logging.basicConfig(level=logging.INFO, format='%(levelname)s:: %(message)s') + +def make_sverilog(instr_dict): + names_str = '' + for i in instr_dict: + names_str += f" localparam [31:0] {i.upper().replace('.','_'):<18s} = 32'b{instr_dict[i]['encoding'].replace('-','?')};\n" + names_str += ' /* CSR Addresses */\n' + for num, name in csrs+csrs32: + names_str += f" localparam logic [11:0] CSR_{name.upper()} = 12'h{hex(num)[2:]};\n" + + sverilog_file = open('inst.sverilog','w') + sverilog_file.write(f''' +/* Automatically generated by parse_opcodes */ +package riscv_instr; +{names_str} +endpackage +''') + sverilog_file.close()
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