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| author | Mladen Slijepcevic <77167949+mslijepc@users.noreply.github.com> | 2025-10-14 00:50:12 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-10-13 15:50:12 -0700 |
| commit | 433081c02368eb72e6dea5413e404a8ef231658e (patch) | |
| tree | e383fdf1c50d44f7329279e5256741c05c20f444 /src/riscv_opcodes/sverilog_utils.py | |
| parent | 56546ec382a8ca6f3f8c7c22ea64862475e0d352 (diff) | |
| download | riscv-opcodes-433081c02368eb72e6dea5413e404a8ef231658e.zip riscv-opcodes-433081c02368eb72e6dea5413e404a8ef231658e.tar.gz riscv-opcodes-433081c02368eb72e6dea5413e404a8ef231658e.tar.bz2 | |
updated instruction naming for rv_zvfofp8min (#377)
Diffstat (limited to 'src/riscv_opcodes/sverilog_utils.py')
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