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| author | Joel Sing <joel@sing.id.au> | 2024-06-28 07:00:13 +1000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-06-27 14:00:13 -0700 |
| commit | 5c03ec5c5cfbbfbc1c12475cbd3a20e8d43f7329 (patch) | |
| tree | 9bf5c8207c1633f17c97d8eb08458b8f1c6ce002 /rv_zvks | |
| parent | 5ce8977a5961a6bbfc1638e6676e60489665d882 (diff) | |
| download | riscv-opcodes-5c03ec5c5cfbbfbc1c12475cbd3a20e8d43f7329.zip riscv-opcodes-5c03ec5c5cfbbfbc1c12475cbd3a20e8d43f7329.tar.gz riscv-opcodes-5c03ec5c5cfbbfbc1c12475cbd3a20e8d43f7329.tar.bz2 | |
Include rs1 values in Go instruction opcodes. (#254)
Some of the instructions in the V extension encode part of the opcode
in the rs1 field. These values are not currently included in the Go
instruction opcodes - fix this by adding an rs1 field and populating
it with the relevant values.
Diffstat (limited to 'rv_zvks')
0 files changed, 0 insertions, 0 deletions