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| author | Thomas Hepworth <tomhepworth@hotmail.co.uk> | 2023-10-26 10:42:34 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-26 10:42:34 +0100 |
| commit | 38a31d663cc044731d740520f0091822bafeee4c (patch) | |
| tree | f2496f62be08ecd33394452c1345b7a8fd1eb6fa /rv_zbb | |
| parent | f9ed144c5c61bbe44e59cc47384024905ed37786 (diff) | |
| download | riscv-opcodes-38a31d663cc044731d740520f0091822bafeee4c.zip riscv-opcodes-38a31d663cc044731d740520f0091822bafeee4c.tar.gz riscv-opcodes-38a31d663cc044731d740520f0091822bafeee4c.tar.bz2 | |
Clarified syntax of regular instructions
See https://github.com/riscv/riscv-opcodes/issues/204
Before this change the text implied that bit encodings and variable arguments could not be mixed in the list of instruction arguments.
Signed-off-by: Thomas Hepworth <tomhepworth@hotmail.co.uk>
Diffstat (limited to 'rv_zbb')
0 files changed, 0 insertions, 0 deletions