diff options
| author | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
| commit | 36f37737b8241fca0e3a5a1d18555cb1d406cff8 (patch) | |
| tree | 11f8479f434fee1da06be155edeff0528c7026b7 /rv_s | |
| parent | 71ecf3563997ea9e7e15a3295aecfe773ad9c04e (diff) | |
| parent | bc92b799d9e96b53a0e57e738bff8f12e6e1fc2d (diff) | |
| download | riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.zip riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.gz riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.bz2 | |
Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-formatincoresemi-migration-to-new-format
Diffstat (limited to 'rv_s')
| -rw-r--r-- | rv_s | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -0,0 +1,3 @@ +sfence.vma 11..7=0 rs1 rs2 31..25=0x09 14..12=0 6..2=0x1C 1..0=3 +sret 11..7=0 19..15=0 31..20=0x102 14..12=0 6..2=0x1C 1..0=3 + |