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| author | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 17:30:26 +0530 |
|---|---|---|
| committer | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 17:30:26 +0530 |
| commit | 56147c766f68cf19f826fde0e4897e988d658bcf (patch) | |
| tree | 6818217046789f94a7492d421ee7b308bd26815d /rv64_d | |
| parent | 34edfce7afebfb95f2eab017b939a5ab912696ca (diff) | |
| download | riscv-opcodes-56147c766f68cf19f826fde0e4897e988d658bcf.zip riscv-opcodes-56147c766f68cf19f826fde0e4897e988d658bcf.tar.gz riscv-opcodes-56147c766f68cf19f826fde0e4897e988d658bcf.tar.bz2 | |
migratte D-extension opcodes
- all changes involve re-ordering to preserve order in latex-tables
Diffstat (limited to 'rv64_d')
| -rw-r--r-- | rv64_d | 7 |
1 files changed, 7 insertions, 0 deletions
@@ -0,0 +1,7 @@ +# RV64D additions to RV32D +fcvt.l.d rd rs1 24..20=2 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fcvt.lu.d rd rs1 24..20=3 31..27=0x18 rm 26..25=1 6..2=0x14 1..0=3 +fmv.x.d rd rs1 24..20=0 31..27=0x1C 14..12=0 26..25=1 6..2=0x14 1..0=3 +fcvt.d.l rd rs1 24..20=2 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fcvt.d.lu rd rs1 24..20=3 31..27=0x1A rm 26..25=1 6..2=0x14 1..0=3 +fmv.d.x rd rs1 24..20=0 31..27=0x1E 14..12=0 26..25=1 6..2=0x14 1..0=3 |