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| author | Andrew Waterman <andrew@sifive.com> | 2023-01-12 13:20:38 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2023-01-12 13:25:03 -0800 |
| commit | 37a0ce0f931ebae564a20878126b15530a3f2cc4 (patch) | |
| tree | 24fac6e1004aaa14329b9209a324b00380d57a07 /rv32_i | |
| parent | e96108394230fe7d5c8952e518713dbf88dd2d4f (diff) | |
| download | riscv-opcodes-37a0ce0f931ebae564a20878126b15530a3f2cc4.zip riscv-opcodes-37a0ce0f931ebae564a20878126b15530a3f2cc4.tar.gz riscv-opcodes-37a0ce0f931ebae564a20878126b15530a3f2cc4.tar.bz2 | |
Fix backwards incompatibility introduced by RV128 opcodes in #112
Adding RV128 shift opcodes changed what metadata we emit for SLLI, SRLI,
and SRAI. Thus, downstream tooling that relies on these to connote the
RV64 variants of these instructions is semantically affected.
Fix by reverting SLLI etc. to being the RV64 variants.
Diffstat (limited to 'rv32_i')
| -rw-r--r-- | rv32_i | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -1,3 +1,3 @@ -$pseudo_op rv128_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::slli slli_rv32 rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srli srli_rv32 rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srai srai_rv32 rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 |