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| author | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2022-05-02 14:20:35 -0700 |
| commit | 36f37737b8241fca0e3a5a1d18555cb1d406cff8 (patch) | |
| tree | 11f8479f434fee1da06be155edeff0528c7026b7 /rv32_c | |
| parent | 71ecf3563997ea9e7e15a3295aecfe773ad9c04e (diff) | |
| parent | bc92b799d9e96b53a0e57e738bff8f12e6e1fc2d (diff) | |
| download | riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.zip riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.gz riscv-opcodes-36f37737b8241fca0e3a5a1d18555cb1d406cff8.tar.bz2 | |
Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv-opcodes into incoresemi-migration-to-new-formatincoresemi-migration-to-new-format
Diffstat (limited to 'rv32_c')
| -rw-r--r-- | rv32_c | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -0,0 +1,5 @@ +# quadrant 1 +c.jal c_imm12 1..0=1 15..13=1 +$pseudo_op rv64_c::c.srli c.srli rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=0 +$pseudo_op rv64_c::c.srai c.srai rd_rs1_p c_nzuimm5 1..0=1 15..13=4 12..10=1 +$pseudo_op rv64_c::c.slli c.slli rd_rs1_n0 c_nzuimm6lo 1..0=2 15..12=0 |