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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-18 00:55:07 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2019-11-28 00:10:23 -0800 |
| commit | 90a3e36cebd260e5383db2e6a939748968848fec (patch) | |
| tree | a129744197ded630467a92ba79e7fde7abd7a241 /parse_opcodes | |
| parent | 2b3905ed85371cc4cecb58730ae34502708de701 (diff) | |
| download | riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.zip riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.tar.gz riscv-opcodes-90a3e36cebd260e5383db2e6a939748968848fec.tar.bz2 | |
rvv: add vleb csr register and mstatus.vs field
1. vleb is read-only CSR to keep vector implementation lenght in byte
2. mstatus.vs is similar to mstatus.fs and designed to keep vector extension
state
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'parse_opcodes')
| -rwxr-xr-x | parse_opcodes | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/parse_opcodes b/parse_opcodes index 9ac586e..883b953 100755 --- a/parse_opcodes +++ b/parse_opcodes @@ -118,6 +118,7 @@ csrs = [ (0xC1F, 'hpmcounter31'), (0xC20, 'vl'), (0xC21, 'vtype'), + (0xC22, 'vlenb'), # Standard Supervisor R/W (0x100, 'sstatus'), |