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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:33:25 -0700 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2011-05-15 22:46:06 -0700 |
| commit | f866323c541a6f26ac58cbbded41ea5c9f2b6fa4 (patch) | |
| tree | f98292a8ea4a6b5fda4066476da5449cbf7369f2 /opcodes | |
| parent | 05e0d24dc582a92eae1809451833d5c76335b81a (diff) | |
| download | riscv-opcodes-f866323c541a6f26ac58cbbded41ea5c9f2b6fa4.zip riscv-opcodes-f866323c541a6f26ac58cbbded41ea5c9f2b6fa4.tar.gz riscv-opcodes-f866323c541a6f26ac58cbbded41ea5c9f2b6fa4.tar.bz2 | |
[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes | 196 |
1 files changed, 107 insertions, 89 deletions
@@ -122,6 +122,10 @@ fence.g.cv rd rs1 imm12 9..7=7 6..2=0x0B 1..0=3 # vector scalar instructions stop 31..27=0 26..22=0 21..17=0 16..7=2 6..2=0x1D 1..0=3 utidx rd 26..22=0 21..17=0 16..7=3 6..2=0x1D 1..0=3 +movz rd rs1 rs2 16..7=4 6..2=0x1D 1..0=3 +movn rd rs1 rs2 16..7=5 6..2=0x1D 1..0=3 +fmovz rd rs1 rs2 16..7=6 6..2=0x1D 1..0=3 +fmovn rd rs1 rs2 16..7=7 6..2=0x1D 1..0=3 ei rd 26..22=0 21..17=0 16..7=0 6..2=0x1E 1..0=3 di rd 26..22=0 21..17=0 16..7=1 6..2=0x1E 1..0=3 @@ -210,115 +214,129 @@ fmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x11 1..0=3 fnmsub.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x12 1..0=3 fnmadd.d rd rs1 rs2 rs3 rm 8..7=1 6..2=0x13 1..0=3 -# vector mem instructions +# vector load mem instructions # 3=d # 2=seg 2=w -# 1=st 1=st 1=f 1=s 1=h -# 0=u 0=ld 0=x 0=u 0=b +# 1=st 1=seg 1=f 1=s 1=h +# 0=u 0=etc 0=x 0=u 0=b # ---------------------------------------------------------------------------- -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # unit stride | | | | | | | | # xloads | | | | | | | | -ld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbu.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -sw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -sh.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sb.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlwu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlhu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlbu rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fld.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsd.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fsw.v rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vfld rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # stride | | | | | | | | # xloads | | | | | | | | -ldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbust.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -swst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -shst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sbst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlstwu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlsthu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlstbu rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flwst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsdst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fswst.v rd rs1 rs2 16=0 15..14=0 13..12=1 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vflstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# mem padding type ldst x/f u/s width opcode +# mem padding type seg x/f u/s width opcode # segment | | | | | | | | # xloads | | | | | | | | -ldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -lwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -lwuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 -lhseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -lhuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 -lbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 -lbuseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 -# xstores -sdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 -swseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 -shseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 -sbseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlsegwu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlseghu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlsegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegbu rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -flwseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# fstores -fsdseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 -fswseg.v rd rs1 rs2 16=0 15..14=0 13..12=2 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 +vflsegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflsegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x02 1..0=3 -# ldst x/f u/s width opcode +# seg x/f u/s width opcode # stride segment | | | | | # xloads | | | | | -ldsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -lwsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -lwusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=2 6..2=0x03 1..0=3 -lhsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -lhusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=1 6..2=0x03 1..0=3 -lbsegst.v rd rs1 rs2 rs3 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 -lbusegst.v rd rs1 rs2 rs3 11=0 10=0 9=1 8..7=0 6..2=0x03 1..0=3 -# xstores -sdsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 -swsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 -shsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 -sbsegst.v rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +vlsegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x02 1..0=3 +vlsegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x02 1..0=3 +vlsegstwu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=2 6..2=0x02 1..0=3 +vlsegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x02 1..0=3 +vlsegsthu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=1 6..2=0x02 1..0=3 +vlsegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x02 1..0=3 +vlsegstbu rd rs1 rs2 rs3 11=1 10=0 9=1 8..7=0 6..2=0x02 1..0=3 # floads -fldsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -flwsegst.v rd rs1 rs2 rs3 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 +vflsegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x02 1..0=3 +vflsegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x02 1..0=3 + +# vector store mem instructions +# mem padding type seg x/f u/s width opcode +# unit stride | | | | | | | | +# xstores | | | | | | | | +vsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vsh rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vsb rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfsd rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfsw rd rs1 21..17=0 16=0 15..14=0 13..12=0 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# mem padding type seg x/f u/s width opcode +# stride | | | | | | | | +# xstores | | | | | | | | +vsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssth rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vsstb rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfsstd rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfsstw rd rs1 rs2 16=0 15..14=0 13..12=1 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# mem padding type seg x/f u/s width opcode +# segment | | | | | | | | +# xstores | | | | | | | | +vssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssegh rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vssegb rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=0 9=0 8..7=0 6..2=0x03 1..0=3 +# fstores +vfssegd rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfssegw rd rs1 rs2 16=0 15..14=0 13..12=2 11=0 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# seg x/f u/s width opcode +# stride segment | | | | | +# xstores | | | | | +vssegstd rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=3 6..2=0x03 1..0=3 +vssegstw rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=2 6..2=0x03 1..0=3 +vssegsth rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=1 6..2=0x03 1..0=3 +vssegstb rd rs1 rs2 rs3 11=1 10=0 9=0 8..7=0 6..2=0x03 1..0=3 # fstores -fsdsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 -fswsegst.v rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 - -# vector arithmetic instructions -mov.vv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=0 6..2=0x02 1..0=3 -mov.sv rd rs1 21..17=0 16=1 15=0 14..12=0 11..7=1 6..2=0x02 1..0=3 -mov.su rd rs1 rs2 16=1 15=0 14..12=0 11..7=2 6..2=0x02 1..0=3 -mov.us rd rs1 rs2 16=1 15=0 14..12=0 11..7=3 6..2=0x02 1..0=3 -fmov.vv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=0 6..2=0x02 1..0=3 -fmov.sv rd rs1 21..17=0 16=1 15=1 14..12=0 11..7=1 6..2=0x02 1..0=3 -fmov.su rd rs1 rs2 16=1 15=1 14..12=0 11..7=2 6..2=0x02 1..0=3 -fmov.us rd rs1 rs2 16=1 15=1 14..12=0 11..7=3 6..2=0x02 1..0=3 - -# vector immediate instructions -vcfgivl rd rs1 imm12 9..7=0 6..2=0x1C 1..0=3 -setvl rd rs1 21..10=0 9..7=1 6..2=0x1C 1..0=3 -vf 31..27=0 rs1 imm12 9..7=2 6..2=0x1C 1..0=3 +vfssegstd rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=3 6..2=0x03 1..0=3 +vfssegstw rd rs1 rs2 rs3 11=1 10=1 9=0 8..7=2 6..2=0x03 1..0=3 + +# other vector register instructions +vmvv rd rs1 21..17=0 16..11=0 10..8=0 7=0 6..2=0x1C 1..0=3 +vmsv rd rs1 21..17=0 16..11=1 10..8=0 7=0 6..2=0x1C 1..0=3 +vmst rd rs1 rs2 16..11=2 10..8=0 7=0 6..2=0x1C 1..0=3 +vmts rd rs1 rs2 16..11=3 10..8=0 7=0 6..2=0x1C 1..0=3 +vfmvv rd rs1 21..17=0 16..11=0 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmsv rd rs1 21..17=0 16..11=1 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmst rd rs1 rs2 16..11=2 10..8=1 7=0 6..2=0x1C 1..0=3 +vfmts rd rs1 rs2 16..11=3 10..8=1 7=0 6..2=0x1C 1..0=3 + +# other vector immediate instructions +vvcfgivl rd rs1 imm12 9..8=0 7=1 6..2=0x1C 1..0=3 +vtcfgivl rd rs1 imm12 9..8=1 7=1 6..2=0x1C 1..0=3 +vsetvl rd rs1 21..10=0 9..8=2 7=1 6..2=0x1C 1..0=3 +vf 31..27=0 rs1 imm12 9..8=3 7=1 6..2=0x1C 1..0=3 # compressed instructions c.li cimm6 crd 4..0=0 |