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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-22 19:22:09 -0800 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2021-02-23 22:31:59 -0800 |
| commit | e8f03925cc307427dfda0f2f250980fcd3e2d6cf (patch) | |
| tree | b52d72fcb2cb01a0127151537ee20e0651b68480 /opcodes-rvv | |
| parent | a985a6855443b095fc1463650f08848f70241433 (diff) | |
| download | riscv-opcodes-e8f03925cc307427dfda0f2f250980fcd3e2d6cf.zip riscv-opcodes-e8f03925cc307427dfda0f2f250980fcd3e2d6cf.tar.gz riscv-opcodes-e8f03925cc307427dfda0f2f250980fcd3e2d6cf.tar.bz2 | |
rvv: add vsetivli
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'opcodes-rvv')
| -rw-r--r-- | opcodes-rvv | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/opcodes-rvv b/opcodes-rvv index f23f590..808e6b1 100644 --- a/opcodes-rvv +++ b/opcodes-rvv @@ -4,12 +4,13 @@ # <opcode> is given by specifying one or more range/value pairs: # hi..lo=value or bit=value or arg=value (e.g. 6..2=0x45 10=1 rd=0) # -# <args> is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm11 +# <args> is one of vd, vs3, vs1, vs2, vm, nf, wd, simm5, zimm10, zimm11 # configuration setting # https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc -vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 -vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 +vsetivli 31=1 30=1 zimm10 zimm 14..12=0x7 rd 6..0=0x57 +vsetvli 31=0 zimm11 rs1 14..12=0x7 rd 6..0=0x57 +vsetvl 31=1 30..25=0x0 rs2 rs1 14..12=0x7 rd 6..0=0x57 # # Vector Loads and Store |