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authorNeel Gala <neelgala@incoresemi.com>2022-04-08 17:38:10 +0530
committerNeel Gala <neelgala@incoresemi.com>2022-04-08 20:11:59 +0530
commit88085a5f6bbb74cb434ff62bacc5912f41fb913b (patch)
tree64cade26276a85e63550a6b66461e39dfe075235 /opcodes-rv64c
parent56147c766f68cf19f826fde0e4897e988d658bcf (diff)
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migrate C-extension opcodes (major)
- the previous opcodes used ignore to define immediate fields instead of assigning arg names to it. This is made it difficult to parse and decode the instructions. - this commit assigns unique names to immediate fields in accordance to what has been done elsewhere. Note these names hold no correspondence to the spec and are defined here purely to ease decoding - This commit also splits the instructions which depend on F/D/Q in to their respective files as per new naming convention - c.nop encoding has been changed to include hints as well.
Diffstat (limited to 'opcodes-rv64c')
-rw-r--r--opcodes-rv64c14
1 files changed, 0 insertions, 14 deletions
diff --git a/opcodes-rv64c b/opcodes-rv64c
deleted file mode 100644
index 7efc7c5..0000000
--- a/opcodes-rv64c
+++ /dev/null
@@ -1,14 +0,0 @@
-# RV64C additions to RVC
-
-# C0 encoding space
-@c.ld 1..0=0 15..13=3 12=ignore 11..2=ignore # c.flw for RV32
-@c.sd 1..0=0 15..13=7 12=ignore 11..2=ignore # c.fsw for RV32
-
-# C1 encoding space
-c.subw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=0 4..2=ignore
-c.addw 1..0=1 15..13=4 12=1 11..10=3 9..7=ignore 6..5=1 4..2=ignore
-@c.addiw 1..0=1 15..13=1 12=ignore 11..2=ignore # c.jal for RV32
-
-# C2 encoding space
-@c.ldsp 1..0=2 15..13=3 12=ignore 11..2=ignore # c.flwsp for RV32
-@c.sdsp 1..0=2 15..13=7 12=ignore 11..2=ignore # c.fswsp for RV32