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| author | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 19:14:00 +0530 |
|---|---|---|
| committer | Neel Gala <neelgala@incoresemi.com> | 2022-04-08 20:11:59 +0530 |
| commit | 98ef45900fbdbe1edf0ce9220e08d60b2912233e (patch) | |
| tree | 6db9d9408cbf331f34299d6e53d187241aa9f856 /opcodes-rv32zk | |
| parent | 9a255844c2726ed301fd4fc9371489f4901d30b0 (diff) | |
| download | riscv-opcodes-98ef45900fbdbe1edf0ce9220e08d60b2912233e.zip riscv-opcodes-98ef45900fbdbe1edf0ce9220e08d60b2912233e.tar.gz riscv-opcodes-98ef45900fbdbe1edf0ce9220e08d60b2912233e.tar.bz2 | |
migrate Zk*-extension opcodes (major)
- significant restructuring of opcodes into files as per new file naming policy
Diffstat (limited to 'opcodes-rv32zk')
| -rw-r--r-- | opcodes-rv32zk | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/opcodes-rv32zk b/opcodes-rv32zk deleted file mode 100644 index 56ed607..0000000 --- a/opcodes-rv32zk +++ /dev/null @@ -1,20 +0,0 @@ - -# -# This file contains opcode specifications for the RISC-V -# Scalar Cryptographic instruction set extension. -# These instructions appear _only_ in RV32. -# ------------------------------------------------------------ - -# Scalar AES - RV32 -aes32esmi rd rs1 rs2 bs 29..25=0b10011 14..12=0 6..0=0x33 -aes32esi rd rs1 rs2 bs 29..25=0b10001 14..12=0 6..0=0x33 -aes32dsmi rd rs1 rs2 bs 29..25=0b10111 14..12=0 6..0=0x33 -aes32dsi rd rs1 rs2 bs 29..25=0b10101 14..12=0 6..0=0x33 - -# Scalar SHA512 - RV32 -sha512sum0r rd rs1 rs2 31..30=1 29..25=0b01000 14..12=0 6..0=0x33 -sha512sum1r rd rs1 rs2 31..30=1 29..25=0b01001 14..12=0 6..0=0x33 -sha512sig0l rd rs1 rs2 31..30=1 29..25=0b01010 14..12=0 6..0=0x33 -sha512sig0h rd rs1 rs2 31..30=1 29..25=0b01110 14..12=0 6..0=0x33 -sha512sig1l rd rs1 rs2 31..30=1 29..25=0b01011 14..12=0 6..0=0x33 -sha512sig1h rd rs1 rs2 31..30=1 29..25=0b01111 14..12=0 6..0=0x33 |