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| author | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-14 23:09:16 -0700 |
|---|---|---|
| committer | Chih-Min Chao <chihmin.chao@sifive.com> | 2020-07-27 00:15:26 -0700 |
| commit | 75f44b5b949922813b7ab971d5ececf863592b0a (patch) | |
| tree | d0485bdb2dce5fb7b548d5a3449d89c609436360 /opcodes-rv32m | |
| parent | 0c0659e1866f04471d57b2dc678a11dd7da67576 (diff) | |
| download | riscv-opcodes-75f44b5b949922813b7ab971d5ececf863592b0a.zip riscv-opcodes-75f44b5b949922813b7ab971d5ececf863592b0a.tar.gz riscv-opcodes-75f44b5b949922813b7ab971d5ececf863592b0a.tar.bz2 | |
rvv: add eew 128 ~ 1024 load/store opcode
spike doesn't implement them but the disassembler use it
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
Diffstat (limited to 'opcodes-rv32m')
0 files changed, 0 insertions, 0 deletions