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| author | Andrew Waterman <andrew@sifive.com> | 2020-03-25 12:28:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2020-03-25 12:28:35 -0700 |
| commit | af61a81535e6ee3fa486057f0d2dbca04a8bd5b7 (patch) | |
| tree | 228ebedbe40fd98e58d430cfa87323d37b36160c /opcodes-rv32d-zfh | |
| parent | 0ce3ec1f7d82d5449ba5d00302270076f6cc34f6 (diff) | |
| download | riscv-opcodes-af61a81535e6ee3fa486057f0d2dbca04a8bd5b7.zip riscv-opcodes-af61a81535e6ee3fa486057f0d2dbca04a8bd5b7.tar.gz riscv-opcodes-af61a81535e6ee3fa486057f0d2dbca04a8bd5b7.tar.bz2 | |
Add tentative RV32Zfh encodingzfh
This is just a placeholder; it may well change before standardization.
Diffstat (limited to 'opcodes-rv32d-zfh')
| -rw-r--r-- | opcodes-rv32d-zfh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes-rv32d-zfh b/opcodes-rv32d-zfh new file mode 100644 index 0000000..02071ad --- /dev/null +++ b/opcodes-rv32d-zfh @@ -0,0 +1,2 @@ +fcvt.h.d rd rs1 24..20=1 31..27=0x08 rm 26..25=2 6..2=0x14 1..0=3 +fcvt.d.h rd rs1 24..20=2 31..27=0x08 rm 26..25=1 6..2=0x14 1..0=3 |