riscv-opcodes.git - Unnamed repository; edit this file 'description' to name the repository.

Branch	Commit message	Author	Age
debug	Update the debug CSR definitions for the proposed 0.13 debug spec	Palmer Dabbelt	8 years
incoresemi-migration-to-new-format	Merge branch 'migration-to-new-format' of https://github.com/incoresemi/riscv...	Andrew Waterman	3 years
master	Merge pull request #316 from Myrausman/repo_structure	Andrew Waterman	4 days
riscv-bitmanip	Remove subu.w	Andrew Waterman	4 years
rnmi	Add RNMI CSRs and instruction	Andrew Waterman	3 years
rvv	Fix config imms	Colin Schmidt	6 years
v	CSRRx is called Zicsr	Andrew Waterman	6 years
vadc	Update encoding of vadc and friends	Andrew Waterman	5 years
wfmi	Add wfmi instruction	Andrew Waterman	3 years
zfh	Add tentative RV32Zfh encoding	Andrew Waterman	5 years
[...]


Age	Commit message	Author	Files	Lines
2020-03-25	Add tentative RV32Zfh encodingzfh	Andrew Waterman	5	-1/+46
2020-03-03	Factor out RVC opcodes into per-extension files	Andrew Waterman	6	-31/+37
2020-03-03	Factor out opcodes into per-extension files	Andrew Waterman	16	-249/+264
2020-03-03	Clean up Makefile	Andrew Waterman	1	-9/+12
2020-02-28	Add mcountinhibit CSR	Andrew Waterman	1	-0/+1
2020-02-24	Add N-extension CSRs and status bits. (#37)	michael-roe	2	-0/+11
2020-02-13	Remove mstatus.HPP; move mstatus.VS to its old location	Andrew Waterman	1	-3/+2
2019-11-28	Remove vamoq; replace vamod with vamo*e	Andrew Waterman	1	-19/+9
2019-11-28	Add vmv<nf>r.v	Andrew Waterman	2	-0/+6
2019-11-28	Merge branch 'chihminchao-rvv-0.8-draft-20191118'	Andrew Waterman	3	-20/+37
[...]