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| author | Andrew Waterman <andrew@sifive.com> | 2024-08-23 17:16:01 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-23 17:16:01 -0500 |
| commit | 290792c1dd51cd23dacb12113f10567a9ede2a98 (patch) | |
| tree | b2fb6c17d4871ba760b89c7f24d6e9956c04f6e7 /c_utils.py | |
| parent | 41c6b4dd2177554e6476ad51f9d0cff8423bf356 (diff) | |
| parent | 62842a38e7d69e69db5b0285be187c57eac51114 (diff) | |
| download | riscv-opcodes-290792c1dd51cd23dacb12113f10567a9ede2a98.zip riscv-opcodes-290792c1dd51cd23dacb12113f10567a9ede2a98.tar.gz riscv-opcodes-290792c1dd51cd23dacb12113f10567a9ede2a98.tar.bz2 | |
Merge pull request #277 from foss-for-synopsys-dwc-arc-processors/PseudoinstructionsAdded
Add some Pseudo Instructions from the ISA and ASM manual
Diffstat (limited to 'c_utils.py')
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