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author | Christian Herber <christian.herber@oss.nxp.com> | 2025-07-17 22:30:45 +0200 |
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committer | GitHub <noreply@github.com> | 2025-07-17 13:30:45 -0700 |
commit | f153a04d58bd13f9d6a23f36360c29a6cfa20dcc (patch) | |
tree | b3cc37169323d4ab0e3f1e16cf540260dc7313e6 | |
parent | c2cd58c7e491534127952a5cd0f098b007048b25 (diff) | |
download | riscv-opcodes-f153a04d58bd13f9d6a23f36360c29a6cfa20dcc.zip riscv-opcodes-f153a04d58bd13f9d6a23f36360c29a6cfa20dcc.tar.gz riscv-opcodes-f153a04d58bd13f9d6a23f36360c29a6cfa20dcc.tar.bz2 |
Adding Zilsd and Zcmlsd extension (#250)
* Adding Zilsd extension
* Renamed Zcmlsd to Zclsd following change from v0.9 to v0.10
-rw-r--r-- | arg_lut.csv | 6 | ||||
-rw-r--r-- | constants.py | 7 | ||||
-rw-r--r-- | unratified/rv32_zclsd | 10 | ||||
-rw-r--r-- | unratified/rv32_zilsd | 4 |
4 files changed, 27 insertions, 0 deletions
diff --git a/arg_lut.csv b/arg_lut.csv index ed30b11..de195d6 100644 --- a/arg_lut.csv +++ b/arg_lut.csv @@ -97,3 +97,9 @@ "c_rs2", 6, 2 "c_sreg1", 9, 7 "c_sreg2", 4, 2 +"rd_p_e", 4, 3 +"rs2_p_e", 4, 3 +"rd_n0_e", 11, 8 +"c_rs2_e", 6, 3 +"rd_e", 11, 8 +"rs2_e", 24, 21
\ No newline at end of file diff --git a/constants.py b/constants.py index fa59aa7..b7b09fd 100644 --- a/constants.py +++ b/constants.py @@ -146,6 +146,13 @@ latex_mapping = { "c_uimm9sp_s": "uimm[5:3$\\vert$8:6]", } +latex_mapping['rd_p_e'] = "rd\\,$'$, even values only" +latex_mapping['rs2_p_e'] = "rs2\\,$'$, even values only" +latex_mapping['rd_n0_e'] = 'rd$\\neq$0, even values only' +latex_mapping['c_rs2_e'] = 'rs2, even values only' +latex_mapping['rd_e'] = 'rd, even values only' +latex_mapping['rs2_e'] = 'rs2, even values only' + # created a dummy instruction-dictionary like dictionary for all the instruction # types so that the same logic can be used to create their tables latex_inst_type = { diff --git a/unratified/rv32_zclsd b/unratified/rv32_zclsd new file mode 100644 index 0000000..b4046eb --- /dev/null +++ b/unratified/rv32_zclsd @@ -0,0 +1,10 @@ +# Compressed load/store pair for RV32 + +# quadrant 0 +$pseudo_op rv32_c_f::c.flw c.ld rd_p_e rs1_p c_uimm8lo c_uimm8hi 2..0=0 15..13=3 +$pseudo_op rv32_c_f::c.fsw c.sd rs1_p rs2_p_e c_uimm8hi c_uimm8lo 2..0=0 15..13=7 + +#quadrant 2 +$pseudo_op rv32_c_f::c.flwsp c.ldsp rd_n0_e c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 7=0 +$pseudo_op rv32_c_f::c.fswsp c.sdsp c_rs2_e c_uimm9sp_s 2..0=2 15..13=7 + diff --git a/unratified/rv32_zilsd b/unratified/rv32_zilsd new file mode 100644 index 0000000..be4f591 --- /dev/null +++ b/unratified/rv32_zilsd @@ -0,0 +1,4 @@ +# Load/store pair for RV32 + +ld rd_e rs1 imm12 14..12=3 7..2=0x00 1..0=3 +sd imm12hi rs1 rs2_e imm12lo 20=0 14..12=3 6..2=0x08 1..0=3
\ No newline at end of file |