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author | Andrew Waterman <andrew@sifive.com> | 2023-01-12 16:41:14 -0800 |
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committer | GitHub <noreply@github.com> | 2023-01-12 16:41:14 -0800 |
commit | b5714329cd8b2c33e7e4ac13866f54f56192da2f (patch) | |
tree | ba2fd095faec741b0c04daa32e53345f2fad6aa1 | |
parent | c190e55d3135dc995e755d98709173e0c8ea9939 (diff) | |
parent | 9ea414b8ec44fd293df5d9126287831052e92b53 (diff) | |
download | riscv-opcodes-b5714329cd8b2c33e7e4ac13866f54f56192da2f.zip riscv-opcodes-b5714329cd8b2c33e7e4ac13866f54f56192da2f.tar.gz riscv-opcodes-b5714329cd8b2c33e7e4ac13866f54f56192da2f.tar.bz2 |
Merge pull request #153 from riscv/undo-rv128-breakage
Fix backwards incompatibility introduced by RV128 opcodes in #112
-rw-r--r-- | constants.py | 3 | ||||
-rwxr-xr-x | parse.py | 5 | ||||
-rw-r--r-- | rv32_i | 6 | ||||
-rw-r--r-- | rv64_i | 6 | ||||
-rw-r--r-- | unratified/rv128_i | 7 |
5 files changed, 15 insertions, 12 deletions
diff --git a/constants.py b/constants.py index 372d2d3..718b5ee 100644 --- a/constants.py +++ b/constants.py @@ -494,7 +494,7 @@ arg_lut['bimm12hi'] = (31, 25) arg_lut['imm12lo'] = (11, 7) arg_lut['bimm12lo'] = (11, 7) arg_lut['zimm'] = (19, 15) -arg_lut['shamt'] = (26, 20) +arg_lut['shamtq'] = (26, 20) arg_lut['shamtw'] = (24, 20) arg_lut['shamtw4'] = (23, 20) arg_lut['shamtd'] = (25, 20) @@ -592,6 +592,7 @@ latex_mapping['jimm20'] = 'imm[20$\\vert$10:1$\\vert$11$\\vert$19:12]' latex_mapping['zimm'] = 'uimm' latex_mapping['shamtw'] = 'shamt' latex_mapping['shamtd'] = 'shamt' +latex_mapping['shamtq'] = 'shamt' latex_mapping['rd_p'] = "rd\\,$'$" latex_mapping['rs1_p'] = "rs1\\,$'$" latex_mapping['rs2_p'] = "rs2\\,$'$" @@ -956,7 +956,10 @@ if __name__ == "__main__": if '-c' in sys.argv[1:]: instr_dict_c = create_inst_dict(extensions, False, - include_pseudo_ops=['pause', 'prefetch_r', 'prefetch_w', 'prefetch_i']) + include_pseudo_ops=['pause', 'prefetch_r', 'prefetch_w', 'prefetch_i', + 'slli_rv32', 'srli_rv32', 'srai_rv32', + 'slli_rv128', 'srli_rv128', 'srai_rv128', + ]) instr_dict_c = collections.OrderedDict(sorted(instr_dict_c.items())) make_c(instr_dict_c) logging.info('encoding.out.h generated successfully') @@ -1,3 +1,3 @@ -$pseudo_op rv128_i::slli slli rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srli srli rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srai srai rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::slli slli_rv32 rd rs1 shamtw 31..25=0 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srli srli_rv32 rd rs1 shamtw 31..25=0 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv128_i::srai srai_rv32 rd rs1 shamtw 31..25=32 14..12=5 6..2=0x04 1..0=3 @@ -4,9 +4,9 @@ lwu rd rs1 imm12 14..12=6 6..2=0x00 1..0=3 ld rd rs1 imm12 14..12=3 6..2=0x00 1..0=3 sd imm12hi rs1 rs2 imm12lo 14..12=3 6..2=0x08 1..0=3 -$pseudo_op rv128_i::slli slli rd rs1 31..26=0 shamtd 14..12=1 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srli srli rd rs1 31..26=0 shamtd 14..12=5 6..2=0x04 1..0=3 -$pseudo_op rv128_i::srai srai rd rs1 31..26=16 shamtd 14..12=5 6..2=0x04 1..0=3 +slli rd rs1 31..26=0 shamtd 14..12=1 6..2=0x04 1..0=3 +srli rd rs1 31..26=0 shamtd 14..12=5 6..2=0x04 1..0=3 +srai rd rs1 31..26=16 shamtd 14..12=5 6..2=0x04 1..0=3 addiw rd rs1 imm12 14..12=0 6..2=0x06 1..0=3 slliw rd rs1 31..25=0 shamtw 14..12=1 6..2=0x06 1..0=3 diff --git a/unratified/rv128_i b/unratified/rv128_i index 1d62fe5..191d61a 100644 --- a/unratified/rv128_i +++ b/unratified/rv128_i @@ -16,7 +16,6 @@ ldu rd rs1 imm12 14..12=7 6..2=0x00 1..0=3 sq imm12hi rs1 rs2 imm12lo 14..12=4 6..2=0x08 1..0=3 -# RV32 and RV64 versions of these are in opcodes-pseudo -slli rd rs1 31..27=0 shamt 14..12=1 6..2=0x04 1..0=3 -srli rd rs1 31..27=0 shamt 14..12=5 6..2=0x04 1..0=3 -srai rd rs1 31..27=8 shamt 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::slli slli_rv128 rd rs1 31..27=0 shamtq 14..12=1 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srli srli_rv128 rd rs1 31..27=0 shamtq 14..12=5 6..2=0x04 1..0=3 +$pseudo_op rv64_i::srai srai_rv128 rd rs1 31..27=8 shamtq 14..12=5 6..2=0x04 1..0=3 |