diff options
| author | Andrew Waterman <andrew@sifive.com> | 2024-08-21 15:35:35 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-21 15:35:35 -0500 |
| commit | 7206bf6c551fb32aa8c7f94c39da88f447f1ca20 (patch) | |
| tree | 2e8cea60223703be2d5eb9266ab261a21729f8cc | |
| parent | 7511f48ffe33f175811efd620684aaa52ffba6d6 (diff) | |
| parent | f55289b7c1d5fc4250a34b50bb75e0be225fd96a (diff) | |
| download | riscv-opcodes-7206bf6c551fb32aa8c7f94c39da88f447f1ca20.zip riscv-opcodes-7206bf6c551fb32aa8c7f94c39da88f447f1ca20.tar.gz riscv-opcodes-7206bf6c551fb32aa8c7f94c39da88f447f1ca20.tar.bz2 | |
Merge pull request #275 from foss-for-synopsys-dwc-arc-processors/UpdateDB
Zicntr was inside Zicsr file
| -rw-r--r-- | rv32_zicntr | 4 | ||||
| -rw-r--r-- | rv_zicntr | 5 | ||||
| -rw-r--r-- | rv_zicsr | 6 |
3 files changed, 9 insertions, 6 deletions
diff --git a/rv32_zicntr b/rv32_zicntr new file mode 100644 index 0000000..2744bb2 --- /dev/null +++ b/rv32_zicntr @@ -0,0 +1,4 @@ +$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3
+
diff --git a/rv_zicntr b/rv_zicntr new file mode 100644 index 0000000..deecaa0 --- /dev/null +++ b/rv_zicntr @@ -0,0 +1,5 @@ +#rv_zicntr instructions
+$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3
+
@@ -13,11 +13,5 @@ $pseudo_op rv_zicsr::csrrw fsrm rd rs1 31..20=0x002 14..12=1 6..2=0x $pseudo_op rv_zicsr::csrrwi fsrmi rd zimm 31..20=0x002 14..12=5 6..2=0x1C 1..0=3 $pseudo_op rv_zicsr::csrrw fscsr rd rs1 31..20=0x003 14..12=1 6..2=0x1C 1..0=3 $pseudo_op rv_zicsr::csrrs frcsr rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycle rd 19..15=0 31..20=0xC00 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtime rd 19..15=0 31..20=0xC01 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstret rd 19..15=0 31..20=0xC02 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdcycleh rd 19..15=0 31..20=0xC80 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdtimeh rd 19..15=0 31..20=0xC81 14..12=2 6..2=0x1C 1..0=3 -$pseudo_op rv_zicsr::csrrs rdinstreth rd 19..15=0 31..20=0xC82 14..12=2 6..2=0x1C 1..0=3 |